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| hitachi 16-bit single-chip microcomputer h8s/2214, h8s/2214 f-ztat? hardware manual ade-602-213a rev. 2.0 7/26/01 hitachi ltd.
cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. preface this lsi is a single-chip microcomputer made up of the h8s/2000 cpu with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. this lsi is equipped with rom, ram, a bus controller, data transfer controller (dtc), a dma controller (dmac), two types of timers, a serial communication interface (sci), a d/a converter, an a/d converter, and i/o ports as on-chip supporting modules. this lsi is suitable for use as an embedded processor for high-level control systems. its on-chip rom are flash memory (f- ztat?*) and mask rom that provides flexibility as it can be reprogrammed in no time to cope with all situations from the early stages of mass production to full-scale mass production. this is particularly applicable to application devices with specifications that will most probably change. note: * f-ztat? is a trademark of hitachi, ltd. target users: this manual was written for users who will be using the h8s/2214, h8s/2214f- ztat? in the design of application systems. members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. objective: this manual was written to explain the hardware functions and electrical characteristics of the h8s/2214, h8s/2214f-ztat? to the above audience. refer to the h8s/2600 series, h8s/2000 series programming manual for a detailed description of the instruction set. notes on reading this manual: ? in order to understand the overall functions of the chip read the manual according to the contents. this manual can be roughly categorized into parts on the cpu, system control functions, peripheral functions and electrical characteristics. ? in order to understand the details of the cpu's functions read the h8s/2600 series, h8s/2000 series programming manual. ? in order to understand the details of a register when its name is known the addresses, bits, and initial values of the registers are summarized in appendix b, internal i/o registers. example: bit order: the msb is on the left and the lsb is on the right. related manuals: the latest versions of all related manuals are available from our web site. please ensure you have the latest versions of all documents you require. http://www.hitachi.co.jp/sicd/english/products/micome.htm h8s/2214, h8s/2214f-ztat? manuals: manual title ade no. h8s/2214, h8s/2214f-ztat? hardware manual this manual h8s/2600 series, h8s/2000 series programming manual ade-602-083 users manuals for development tools: manual title ade no. c/c++ complier, assembler, optimized linkage editor user's manual ade-702-247 simulator debugger (for windows) users manual ade-702-037 hitachi embedded workshop users manual ade-702-201 application notes: manual title ade no. h8s series technical q & a ade-502-059 list of items revised or added for this version section title page revisions (see manual for details) section 1 overview 1.1 overview 2 table 1-1 overview description of dma controller (dmac) amended. 1.2 internal block diagrams 5 figure 1-1 h8s/2214 internal block diagram amended. 1.3.1 pin arrangements 6 figure 1-2 h8s/2214 pin arrangement (tfp-100b, tfp- 100g: top view) amended. 1.3.2 pin functions in each operating mode 9 table 1-2 pin functions in each operating mode mode of pin nos. 34 and 35 revised from 4 to 7. 1.3.3 pin functions 14 table 1-3 pin functions. description of dma controller (dmac) amended. section 7 dma 7.1.1 features 163 description of short address mode amended. controller 7.1.2 block diagram 164 figure 7-1 block diagram of dmac amended. 7.1.3 overview of functions 165 table 7-1 overview of dmac functions (short address mode) description of single address mode deleted. 7.1.4 pin configuration 167 description of pin configuration amended. table 7-3 dmac pins amended. 7.2.4 dma control register (dmacr) 173 description of bit 4: data transfer direction (dtdir) amended, and table amended. 7.2.5 dma band control register (dmabcr) 176 dmabcrh of bits 13 and 12 changed to "." bits 13 and 12reserved bits. description of 12 and 13 grouped together. 7.3.5 dma band control register (dmabcr) 189 revised as follows: bits 10 and 8reserved (dta1a, dta0a): reserved bits in full address mode. read and write possible. section title page revisions (see manual for details) section 7 7.5 operation 7.5.5 single address mode deleted. dma controller 7.5.11 dmac bus cycles (single address mode) deleted. 7.5.12 write data buffer function deleted. 7.5.1 transfer modes 196 table 7-6 dmac transfer modes single address mode deleted. note revise. description of single address mode deleted. 7.5.7 dmac activation sources description of single address mode deleted. 7.5.11 relation between the dmac, external bus requests, and the dtc 229 description of refresh cycle deleted. 7.7 usage notes 235 module stop description of dack pin enable (fae=0 and sae=1) deleted. write data buffer function deleted. section 9 i/o ports 9.1 overview 266 table 9-1 h8s/2214 port functions description of port 1 dmac output pins (dack0 and dack1) deleted. 269 description of dmac output pins (dack0 and dack1) related to port 1 deleted. section 10 16-bit timer pulse unit (tpu) 10.1.2 block diagram 345 figure 10-1 block diagram of h8s/2214 tpu a/d conversion start request signal deleted. section 11 watchdog timer (wdt) 11.2.2 timer control/status register (tcsr) 419 table bit 7: overflow flag (ovh) amended and note added. 11.2.4 notes on register access 422 writing to rstcsr h'ffbb in description changed to h'ff76. section title page revisions (see manual for details) section 15 rom 15.4.3 mode transitions 522 pf3=1 added to notes: 2 in figure 15-3 flash memory state transitions. 15.13 flash memory programmer mode 557 pf3 added to table 15-12 programmer mode pin settings. 15.13.1 socket adapter pin correspondence diagram 558 figure 15-20 socket adapter pin correspondence diagram amended. section 18 electrical characteristics 18.1 absolute maximum ratings 603 preliminary deleted from table 18-1 absolute maximum ratings. 18.2 power supply voltage and operating frequency range 604 preliminary deleted from figure 18-1 power supply voltage and operating frequency range. 18.3 dc characteristics 605 table 18-2 dc characteristics (1) amended. preliminary deleted. 607 table 18-3 dc characteristics (2) amended. preliminary deleted, and notes amended. 608 table 18-4 dc characteristics (3) amended. preliminary deleted, and notes amended. 609 preliminary deleted from table 18-5 permissible output currents. 18.4.1 clock timing 610 preliminary deleted from table 18-6 clock timing. 18.4.2 control signal timing 611 preliminary deleted from table 18-7 control signal timing. 18.4.3 bus timing 613, 614 table 18-8 bus timing amended. preliminary deleted. 18.4.4 timing of on-chip supporting modules 620 table 18-9 timing of on-chip supporting modules amended. preliminary deleted. 18.4.5 dmac timing 623 added. 18.5 d/a convervion characteristics 624 preliminary deleted from table 18- 11 d/a conversion characteristics. section title page revisions (see manual for details) section 18 electrical characteristics 18.6 flash memory characteristics 625 table 18-12 flash memory characteristics amended. preliminary deleted. appendix b.1 address 707 address h'ff66 bits 5 and 4 revised to "." b.2 functions 764 address h'ff66 bits 13 and 12 revised note added. f product code lineup 826 table f-1 h8s/2214 product code lineup amended. i contents section 1 overview ............................................................................................................ 1 1.1 overview ................................................................................................................... ......... 1 1.2 internal block diagrams .................................................................................................... 5 1.3 pin description ............................................................................................................ ....... 6 1.3.1 pin arrangements.................................................................................................. 6 1.3.2 pin functions in each operating mode ................................................................ 8 1.3.3 pin functions......................................................................................................... 12 section 2 cpu ...................................................................................................................... 17 2.1 overview ................................................................................................................... ......... 17 2.1.1 features ................................................................................................................. 17 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu ................................... 18 2.1.3 differences from h8/300 cpu.............................................................................. 19 2.1.4 differences from h8/300h cpu........................................................................... 19 2.2 cpu operating modes ....................................................................................................... 2 0 2.3 address space .............................................................................................................. ...... 25 2.4 register configuration ..................................................................................................... .. 2 6 2.4.1 overview ............................................................................................................... 26 2.4.2 general registers .................................................................................................. 27 2.4.3 control registers................................................................................................... 28 2.4.4 initial register values ........................................................................................... 30 2.5 data formats ............................................................................................................... ....... 31 2.5.1 general register data formats ............................................................................. 31 2.5.2 memory data formats .......................................................................................... 33 2.6 instruction set ............................................................................................................ ........ 34 2.6.1 overview ............................................................................................................... 34 2.6.2 instructions and addressing modes ...................................................................... 35 2.6.3 table of instructions classified by function ........................................................ 37 2.6.4 basic instruction formats...................................................................................... 47 2.6.5 notes on use of bit-manipulation instructions .................................................... 48 2.7 addressing modes and effective address calculation...................................................... 48 2.7.1 addressing mode .................................................................................................. 48 2.7.2 effective address calculation............................................................................... 51 2.8 processing states .......................................................................................................... ...... 55 2.8.1 overview ............................................................................................................... 55 2.8.2 reset state ............................................................................................................. 5 6 2.8.3 exception-handling state ..................................................................................... 57 2.8.4 program execution state ....................................................................................... 60 2.8.5 bus-released state................................................................................................ 60 ii 2.8.6 power-down state ................................................................................................ 60 2.9 basic timing ............................................................................................................... ....... 61 2.9.1 overview ............................................................................................................... 61 2.9.2 on-chip memory (rom, ram) .......................................................................... 61 2.9.3 on-chip supporting module access timing........................................................ 63 2.9.4 external address space access timing................................................................ 64 2.10 usage note ................................................................................................................ ......... 64 section 3 mcu operating modes ................................................................................. 65 3.1 overview ................................................................................................................... ......... 65 3.1.1 operating mode selection .................................................................................... 65 3.1.2 register configuration .......................................................................................... 66 3.2 register descriptions...................................................................................................... .... 66 3.2.1 mode control register (mdcr) .......................................................................... 66 3.2.2 system control register (syscr) ....................................................................... 67 3.3 operating mode descriptions ............................................................................................ 69 3.3.1 mode 4 .................................................................................................................. 6 9 3.3.2 mode 5 .................................................................................................................. 6 9 3.3.3 mode 6 .................................................................................................................. 7 0 3.3.4 mode 7 .................................................................................................................. 7 0 3.4 pin functions in each operating mode.............................................................................. 71 3.5 memory map in each operating mode.............................................................................. 71 section 4 exception handling ........................................................................................ 73 4.1 overview ................................................................................................................... ......... 73 4.1.1 exception handling types and priority................................................................ 73 4.1.2 exception handling operation.............................................................................. 74 4.1.3 exception sources and vector table .................................................................... 74 4.2 reset ...................................................................................................................... ............. 76 4.2.1 overview ............................................................................................................... 76 4.2.2 reset types ........................................................................................................... 76 4.2.3 reset sequence...................................................................................................... 77 4.2.4 interrupts after reset ............................................................................................. 79 4.2.5 state of on-chip supporting modules after reset release .................................. 79 4.3 traces ..................................................................................................................... ............ 80 4.4 interrupts ................................................................................................................. ........... 81 4.5 trap instruction ........................................................................................................... ....... 82 4.6 stack status after exception handling ............................................................................... 83 4.7 notes on use of the stack .................................................................................................. 84 section 5 interrupt controller ......................................................................................... 85 5.1 overview ................................................................................................................... ......... 85 5.1.1 features ................................................................................................................. 85 iii 5.1.2 block diagram ...................................................................................................... 86 5.1.3 pin configuration .................................................................................................. 87 5.1.4 register configuration .......................................................................................... 87 5.2 register descriptions...................................................................................................... .... 88 5.2.1 system control register (syscr) ....................................................................... 88 5.2.2 interrupt priority registers a to d, f, g, j, k, m (ipra to iprd, iprf, iprg, iprj, iprk, iprm) .............................................. 89 5.2.3 irq enable register (ier) ................................................................................... 90 5.2.4 irq sense control registers h and l (iscrh, iscrl)...................................... 91 5.2.5 irq status register (isr) ..................................................................................... 92 5.3 interrupt sources .......................................................................................................... ...... 93 5.3.1 external interrupts................................................................................................. 93 5.3.2 internal interrupts.................................................................................................. 94 5.3.3 interrupt exception handling vector table.......................................................... 94 5.4 interrupt operation ........................................................................................................ ..... 97 5.4.1 interrupt control modes and interrupt operation ................................................. 97 5.4.2 interrupt control mode 0 ...................................................................................... 100 5.4.3 interrupt control mode 2 ...................................................................................... 102 5.4.4 interrupt exception handling sequence ............................................................... 104 5.4.5 interrupt response times...................................................................................... 105 5.5 usage notes................................................................................................................ ........ 106 5.5.1 contention between interrupt generation and disabling...................................... 106 5.5.2 instructions that disable interrupts ....................................................................... 107 5.5.3 times when interrupts are disabled...................................................................... 107 5.5.4 interrupts during execution of eepmov instruction .......................................... 107 5.6 dtc and dmac activation by interrupt .......................................................................... 108 5.6.1 overview ............................................................................................................... 10 8 5.6.2 block diagram ...................................................................................................... 108 5.6.3 operation ............................................................................................................... 1 09 section 6 bus controller .................................................................................................. 111 6.1 overview ................................................................................................................... ......... 111 6.1.1 features ................................................................................................................. 111 6.1.2 block diagram ...................................................................................................... 112 6.1.3 pin configuration .................................................................................................. 113 6.1.4 register configuration .......................................................................................... 114 6.2 register descriptions...................................................................................................... .... 115 6.2.1 bus width control register (abwcr)................................................................ 115 6.2.2 access state control register (astcr) .............................................................. 116 6.2.3 wait control registers h and l (wcrh, wcrl) .............................................. 117 6.2.4 bus control register h (bcrh) .......................................................................... 121 6.2.5 bus control register l (bcrl)............................................................................ 123 6.2.6 pin function control register (pfcr) ................................................................. 124 iv 6.3 overview of bus control.................................................................................................... 126 6.3.1 area divisions....................................................................................................... 126 6.3.2 bus specifications ................................................................................................. 127 6.3.3 memory interfaces ................................................................................................ 128 6.3.4 interface specifications for each area.................................................................. 129 6.3.5 chip select signals................................................................................................ 130 6.4 basic bus interface........................................................................................................ ..... 131 6.4.1 overview ............................................................................................................... 13 1 6.4.2 data size and data alignment.............................................................................. 131 6.4.3 valid strobes........................................................................................................ 133 6.4.4 basic timing ......................................................................................................... 134 6.4.5 wait control.......................................................................................................... 142 6.5 burst rom interface ........................................................................................................ .. 144 6.5.1 overview ............................................................................................................... 14 4 6.5.2 basic timing ......................................................................................................... 144 6.5.3 wait control.......................................................................................................... 146 6.6 idle cycle................................................................................................................. ........... 147 6.6.1 operation ............................................................................................................... 1 47 6.6.2 pin states in idle cycle ......................................................................................... 150 6.7 bus release ................................................................................................................ ........ 151 6.7.1 overview ............................................................................................................... 15 1 6.7.2 operation ............................................................................................................... 1 51 6.7.3 pin states in external bus released state ............................................................ 152 6.7.4 transition timing.................................................................................................. 153 6.7.5 usage note ............................................................................................................ 154 6.8 bus arbitration ............................................................................................................ ....... 154 6.8.1 overview ............................................................................................................... 15 4 6.8.2 operation ............................................................................................................... 1 54 6.8.3 bus transfer timing ............................................................................................. 155 6.8.4 external bus release usage note ......................................................................... 155 6.9 resets and the bus controller ............................................................................................ 15 6 6.10 external module expansion function................................................................................ 156 6.10.1 overview ............................................................................................................... 1 56 6.10.2 pin configuration .................................................................................................. 157 6.10.3 register configuration .......................................................................................... 157 6.11 register descriptions..................................................................................................... ..... 158 6.11.1 interrupt request input pin select register 0 (ipinsel0) .................................. 158 6.11.2 external module connection output pin select register (opinsel)................. 160 6.11.3 module stop control register b (mstpcrb)..................................................... 161 6.12 basic timing .............................................................................................................. ........ 162 section 7 dma controller ............................................................................................... 163 7.1 overview ................................................................................................................... ......... 163 v 7.1.1 features ................................................................................................................. 163 7.1.2 block diagram ...................................................................................................... 164 7.1.3 overview of functions.......................................................................................... 165 7.1.4 pin configuration .................................................................................................. 167 7.1.5 register configuration .......................................................................................... 168 7.2 register descriptions (1) (short address mode) ............................................................... 169 7.2.1 memory address registers (mar) ...................................................................... 170 7.2.2 i/o address register (ioar)................................................................................ 171 7.2.3 execute transfer count register (etcr) ............................................................ 171 7.2.4 dma control register (dmacr)........................................................................ 172 7.2.5 dma band control register (dmabcr)............................................................ 176 7.3 register descriptions (2) (full address mode) ................................................................. 181 7.3.1 memory address register (mar)........................................................................ 181 7.3.2 i/o address register (ioar)................................................................................ 181 7.3.3 execute transfer count register (etcr) ............................................................ 182 7.3.4 dma control register (dmacr)........................................................................ 183 7.3.5 dma band control register (dmabcr)............................................................ 187 7.4 register descriptions (3).................................................................................................. .. 192 7.4.1 dma write enable register (dmawer) ........................................................... 192 7.4.2 dma terminal control register (dmatcr)...................................................... 194 7.4.3 module stop control register a (mstpcra) .................................................... 195 7.5 operation .................................................................................................................. .......... 196 7.5.1 transfer modes ..................................................................................................... 196 7.5.2 sequential mode.................................................................................................... 198 7.5.3 idle mode .............................................................................................................. 20 1 7.5.4 repeat mode ......................................................................................................... 204 7.5.5 normal mode ........................................................................................................ 208 7.5.6 block transfer mode ............................................................................................ 211 7.5.7 dmac activation sources ................................................................................... 217 7.5.8 basic dmac bus cycles...................................................................................... 219 7.5.9 dmac bus cycles (dual address mode)............................................................ 220 7.5.10 dmac multi-channel operation ......................................................................... 227 7.5.11 relation between the dmac, external bus requests, and the dtc ................... 229 7.5.12 nmi interrupts and dmac................................................................................... 230 7.5.13 forced termination of dmac operation............................................................. 231 7.5.14 clearing full address mode ................................................................................. 232 7.6 interrupts ................................................................................................................. ........... 233 7.7 usage notes................................................................................................................ ........ 234 section 8 data transfer controller (dtc) ................................................................. 237 8.1 overview ................................................................................................................... ......... 237 8.1.1 features ................................................................................................................. 237 8.1.2 block diagram ...................................................................................................... 238 vi 8.1.3 register configuration .......................................................................................... 239 8.2 register descriptions...................................................................................................... .... 240 8.2.1 dtc mode register a (mra).............................................................................. 240 8.2.2 dtc mode register b (mrb).............................................................................. 242 8.2.3 dtc source address register (sar) ................................................................... 243 8.2.4 dtc destination address register (dar) ........................................................... 243 8.2.5 dtc transfer count register a (cra) ............................................................... 243 8.2.6 dtc transfer count register b (crb)................................................................ 244 8.2.7 dtc enable registers (dtcer) .......................................................................... 244 8.2.8 dtc vector register (dtvecr) ......................................................................... 245 8.2.9 module stop control register a (mstpcra) .................................................... 246 8.3 operation .................................................................................................................. .......... 247 8.3.1 overview ............................................................................................................... 24 7 8.3.2 activation sources ................................................................................................ 249 8.3.3 dtc vector table ................................................................................................. 250 8.3.4 location of register information in address space ............................................. 253 8.3.5 normal mode ........................................................................................................ 253 8.3.6 repeat mode ......................................................................................................... 254 8.3.7 block transfer mode ............................................................................................ 255 8.3.8 chain transfer....................................................................................................... 257 8.3.9 operation timing .................................................................................................. 258 8.3.10 number of dtc execution states ........................................................................ 259 8.3.11 procedures for using dtc.................................................................................... 261 8.3.12 examples of use of the dtc ................................................................................ 262 8.4 interrupts ................................................................................................................. ........... 264 8.5 usage notes................................................................................................................ ........ 264 section 9 i/o ports ............................................................................................................. 265 9.1 overview ................................................................................................................... ......... 265 9.2 port 1 ..................................................................................................................... ............. 269 9.2.1 overview ............................................................................................................... 26 9 9.2.2 register configuration .......................................................................................... 270 9.2.3 pin functions......................................................................................................... 272 9.3 port 3 ..................................................................................................................... ............. 280 9.3.1 overview ............................................................................................................... 28 0 9.3.2 register configuration .......................................................................................... 280 9.3.3 pin functions......................................................................................................... 285 9.4 port 4 ..................................................................................................................... ............. 287 9.4.1 overview ............................................................................................................... 28 7 9.4.2 register configuration .......................................................................................... 287 9.4.3 pin functions......................................................................................................... 290 9.5 port 7 ..................................................................................................................... ............. 291 9.5.1 overview ............................................................................................................... 29 1 vii 9.5.2 register configuration .......................................................................................... 292 9.5.3 pin functions......................................................................................................... 295 9.6 port 9 ..................................................................................................................... ............. 297 9.6.1 overview ............................................................................................................... 29 7 9.6.2 register configuration .......................................................................................... 297 9.6.3 pin functions......................................................................................................... 298 9.7 port a..................................................................................................................... ............. 298 9.7.1 overview ............................................................................................................... 29 8 9.7.2 register configuration .......................................................................................... 299 9.7.3 pin functions......................................................................................................... 301 9.7.4 mos input pull-up function................................................................................ 304 9.8 port b..................................................................................................................... ............. 305 9.8.1 overview ............................................................................................................... 30 5 9.8.2 register configuration .......................................................................................... 306 9.8.3 pin functions......................................................................................................... 308 9.8.4 mos input pull-up function................................................................................ 312 9.9 port c..................................................................................................................... ............. 313 9.9.1 overview ............................................................................................................... 31 3 9.9.2 register configuration .......................................................................................... 314 9.9.3 pin functions in each mode.................................................................................. 316 9.9.4 mos input pull-up function................................................................................ 318 9.10 port d.................................................................................................................... .............. 319 9.10.1 overview ............................................................................................................... 3 19 9.10.2 register configuration .......................................................................................... 320 9.10.3 pin functions in each mode ................................................................................. 322 9.10.4 mos input pull-up function................................................................................ 323 9.11 port e.................................................................................................................... .............. 324 9.11.1 overview ............................................................................................................... 3 24 9.11.2 register configuration .......................................................................................... 325 9.11.3 pin functions in each mode ................................................................................. 327 9.11.4 mos input pull-up function................................................................................ 328 9.12 port f.................................................................................................................... .............. 330 9.12.1 overview ............................................................................................................... 3 30 9.12.2 register configuration .......................................................................................... 331 9.12.3 pin functions......................................................................................................... 33 2 9.13 port g.................................................................................................................... .............. 335 9.13.1 overview ............................................................................................................... 3 35 9.13.2 register configuration .......................................................................................... 336 9.13.3 pin functions......................................................................................................... 33 8 section 10 16-bit timer pulse unit (tpu) ................................................................... 341 10.1 overview .................................................................................................................. .......... 341 10.1.1 features ................................................................................................................ . 341 viii 10.1.2 block diagram ...................................................................................................... 345 10.1.3 pin configuration .................................................................................................. 346 10.1.4 register configuration .......................................................................................... 347 10.2 register descriptions..................................................................................................... ..... 348 10.2.1 timer control register (tcr) .............................................................................. 348 10.2.2 timer mode register (tmdr) ............................................................................. 352 10.2.3 timer i/o control register (tior) ...................................................................... 354 10.2.4 timer interrupt enable register (tier) ............................................................... 361 10.2.5 timer status register (tsr) ................................................................................. 363 10.2.6 timer counter (tcnt) ......................................................................................... 366 10.2.7 timer general register (tgr) ............................................................................. 367 10.2.8 timer start register (tstr)................................................................................. 367 10.2.9 timer synchro register (tsyr) .......................................................................... 368 10.2.10 module stop control register a (mstpcra) .................................................... 369 10.3 interface to bus master .................................................................................................... .. 370 10.3.1 16-bit registers..................................................................................................... 370 10.3.2 8-bit registers....................................................................................................... 370 10.4 operation ................................................................................................................. ........... 372 10.4.1 overview ............................................................................................................... 3 72 10.4.2 basic functions ..................................................................................................... 373 10.4.3 synchronous operation ......................................................................................... 379 10.4.4 buffer operation ................................................................................................... 381 10.4.5 pwm modes ......................................................................................................... 385 10.4.6 phase counting mode ........................................................................................... 390 10.5 interrupts ................................................................................................................ ............ 395 10.5.1 interrupt sources and priorities............................................................................. 395 10.5.2 dtc activation ..................................................................................................... 396 10.6 operation timing .......................................................................................................... ..... 397 10.6.1 input/output timing ............................................................................................. 397 10.6.2 interrupt signal timing ......................................................................................... 401 10.7 usage notes............................................................................................................... ......... 405 section 11 watchdog timer (wdt) ............................................................................... 415 11.1 overview .................................................................................................................. .......... 415 11.1.1 features ................................................................................................................ . 415 11.1.2 block diagram ...................................................................................................... 416 11.1.3 register configuration .......................................................................................... 417 11.2 register descriptions..................................................................................................... ..... 418 11.2.1 timer counter (tcnt) ......................................................................................... 418 11.2.2 timer control/status register (tcsr) ................................................................. 418 11.2.3 reset control/status register (rstcsr) ............................................................. 420 11.2.4 notes on register access...................................................................................... 422 11.3 operation ................................................................................................................. ........... 424 ix 11.3.1 watchdog timer operation .................................................................................. 424 11.3.2 interval timer operation ...................................................................................... 425 11.3.3 timing of setting of overflow flag (ovf).......................................................... 426 11.3.4 timing of setting of watchdog timer overflow flag (wovf).......................... 426 11.4 interrupts ................................................................................................................ ............ 427 11.5 usage notes............................................................................................................... ......... 428 11.5.1 contention between timer counter (tcnt) write and increment...................... 428 11.5.2 changing value of cks2 to cks0....................................................................... 428 11.5.3 switching between watchdog timer mode and interval timer mode ................ 428 11.5.4 internal reset in watchdog timer mode.............................................................. 429 section 12 serial communication interface (sci) ............................................ 431 12.1 overview .................................................................................................................. .......... 431 12.1.1 features ................................................................................................................ . 431 12.1.2 block diagram ...................................................................................................... 433 12.1.3 pin configuration .................................................................................................. 435 12.1.4 register configuration .......................................................................................... 436 12.2 register descriptions..................................................................................................... ..... 437 12.2.1 receive shift register (rsr)................................................................................ 437 12.2.2 receive data register (rdr) ............................................................................... 437 12.2.3 transmit shift register (tsr) .............................................................................. 438 12.2.4 transmit data register (tdr).............................................................................. 438 12.2.5 serial mode register (smr)................................................................................. 439 12.2.6 serial control register (scr)............................................................................... 442 12.2.7 serial status register (ssr).................................................................................. 445 12.2.8 bit rate register (brr)........................................................................................ 449 12.2.9 smart card mode register (scmr) ..................................................................... 457 12.2.10 serial extended mode register 0 (semr0) ......................................................... 458 12.2.11 module stop control register b (mstpcrb)..................................................... 463 12.3 operation ................................................................................................................. ........... 464 12.3.1 overview ............................................................................................................... 4 64 12.3.2 operation in asynchronous mode ........................................................................ 467 12.3.3 multiprocessor communication function ............................................................ 479 12.3.4 operation in clocked synchronous mode ............................................................ 487 12.4 sci interrupts ............................................................................................................ ......... 495 12.5 usage notes............................................................................................................... ......... 497 section 13 d/a converter .................................................................................................. 507 13.1 overview .................................................................................................................. .......... 507 13.1.1 features ................................................................................................................ . 507 13.1.2 block diagram ...................................................................................................... 508 13.1.3 pin configuration .................................................................................................. 509 13.1.4 register configuration .......................................................................................... 509 x 13.2 register descriptions..................................................................................................... ..... 509 13.2.1 d/a data register 0 (dadr0) ............................................................................. 509 13.2.2 d/a control register (dacr).............................................................................. 510 13.2.3 module stop control register c (mstpcrc)..................................................... 510 13.3 operation ................................................................................................................. ........... 511 section 14 ram .................................................................................................................... 513 14.1 overview .................................................................................................................. .......... 513 14.1.1 block diagram ...................................................................................................... 513 14.1.2 register configuration .......................................................................................... 514 14.2 register descriptions..................................................................................................... ..... 514 14.2.1 system control register (syscr) ....................................................................... 514 14.3 operation ................................................................................................................. ........... 515 14.4 usage note ................................................................................................................ ......... 515 section 15 rom .................................................................................................................... 517 15.1 overview .................................................................................................................. .......... 517 15.1.1 block diagram ...................................................................................................... 517 15.1.2 register configuration .......................................................................................... 518 15.2 register descriptions..................................................................................................... ..... 518 15.2.1 mode control register (mdcr) .......................................................................... 518 15.3 operation ................................................................................................................. ........... 519 15.4 overview of flash memory................................................................................................ 52 0 15.4.1 features ................................................................................................................ . 520 15.4.2 block diagram ...................................................................................................... 521 15.4.3 mode transitions .................................................................................................. 522 15.4.4 on-board programming modes............................................................................ 523 15.4.5 flash memory emulation in ram........................................................................ 525 15.4.6 differences between boot mode and user program mode .................................. 526 15.4.7 block divisions ..................................................................................................... 527 15.5 pin configuration ......................................................................................................... ...... 528 15.6 register configuration .................................................................................................... ... 529 15.7 register descriptions..................................................................................................... ..... 530 15.7.1 flash memory control register 1 (flmcr1)...................................................... 530 15.7.2 flash memory control register 2 (flmcr2)...................................................... 533 15.7.3 erase block register 1 (ebr1) ............................................................................ 534 15.7.4 erase block register 2 (ebr2) ............................................................................ 534 15.7.5 ram emulation register (ramer).................................................................... 535 15.7.6 serial control register x (scrx)........................................................................ 536 15.8 on-board programming modes ......................................................................................... 538 15.8.1 boot mode............................................................................................................. 53 8 15.8.2 user program mode .............................................................................................. 543 15.9 programming/erasing flash memory ................................................................................ 545 xi 15.9.1 program mode....................................................................................................... 545 15.9.2 program-verify mode ........................................................................................... 546 15.9.3 erase mode............................................................................................................ 54 8 15.9.4 erase-verify mode................................................................................................ 548 15.10 protection............................................................................................................... ............. 550 15.10.1 hardware protection.............................................................................................. 550 15.10.2 software protection ............................................................................................... 551 15.10.3 error protection ..................................................................................................... 55 2 15.11 flash memory emulation in ram..................................................................................... 554 15.12 interrupt handling when programming/erasing flash memory........................................ 556 15.13 flash memory programmer mode ..................................................................................... 556 15.13.1 socket adapter pin correspondence diagram...................................................... 557 15.13.2 programmer mode operation................................................................................ 559 15.13.3 memory read mode.............................................................................................. 560 15.13.4 auto-program mode.............................................................................................. 563 15.13.5 auto-erase mode .................................................................................................. 565 15.13.6 status read mode.................................................................................................. 567 15.13.7 status polling ........................................................................................................ 5 68 15.13.8 programmer mode transition time...................................................................... 568 15.13.9 notes on memory programming........................................................................... 569 15.14 flash memory and power-down states ............................................................................. 570 15.14.1 note on power-down states ................................................................................. 570 15.15 flash memory programming and erasing precautions...................................................... 571 15.16 note on switching from f-ztat version to mask rom version ................................... 576 section 16 clock pulse generator ................................................................................... 577 16.1 overview .................................................................................................................. .......... 577 16.1.1 block diagram ...................................................................................................... 577 16.1.2 register configuration.......................................................................................... 578 16.2 register descriptions..................................................................................................... ..... 578 16.2.1 system clock control register (sckcr) ............................................................ 578 16.2.2 low-power control register (lpwrcr) ............................................................ 579 16.3 system clock oscillator ................................................................................................... .. 581 16.3.1 connecting a crystal resonator............................................................................ 581 16.3.2 external clock input ............................................................................................. 583 16.4 duty adjustment circuit ................................................................................................... . 586 16.5 medium-speed clock divider............................................................................................ 586 16.6 bus master clock selection circuit ................................................................................... 586 16.7 note on crystal resonator................................................................................................. . 586 section 17 power-down modes ....................................................................................... 587 17.1 overview .................................................................................................................. .......... 587 17.1.1 register configuration .......................................................................................... 590 xii 17.2 register descriptions..................................................................................................... ..... 590 17.2.1 standby control register (sbycr) ..................................................................... 590 17.2.2 system clock control register (sckcr) ............................................................ 592 17.2.3 module stop control register (mstpcr) ........................................................... 593 17.3 medium-speed mode ......................................................................................................... 594 17.4 sleep mode................................................................................................................ ......... 595 17.4.1 sleep mode............................................................................................................ 59 5 17.4.2 clearing sleep mode ............................................................................................. 595 17.5 module stop mode .......................................................................................................... ... 596 17.5.1 module stop mode................................................................................................ 596 17.5.2 usage notes .......................................................................................................... 597 17.6 software standby mode ..................................................................................................... 598 17.6.1 software standby mode........................................................................................ 598 17.6.2 clearing software standby mode ......................................................................... 598 17.6.3 setting oscillation stabilization time after clearing software standby mode ... 599 17.6.4 software standby mode application example ..................................................... 599 17.6.5 usage notes .......................................................................................................... 600 17.7 hardware standby mode.................................................................................................... 6 00 17.7.1 hardware standby mode ...................................................................................... 600 17.7.2 hardware standby mode timing.......................................................................... 601 17.8 ? clock output disabling function.................................................................................... 602 section 18 electrical characteristics ............................................................................... 603 18.1 absolute maximum ratings............................................................................................... 603 18.2 power supply voltage and operating frequency range ................................................... 604 18.3 dc characteristics........................................................................................................ ...... 605 18.4 ac characteristics........................................................................................................ ...... 609 18.4.1 clock timing ........................................................................................................ 610 18.4.2 control signal timing .......................................................................................... 611 18.4.3 bus timing............................................................................................................ 61 3 18.4.4 timing of on-chip supporting modules.............................................................. 620 18.4.5 dmac timing ...................................................................................................... 623 18.5 d/a convervion characteristics ........................................................................................ 624 18.6 flash memory characteristics............................................................................................ 62 5 18.7 usage note ................................................................................................................ ......... 626 appendix a instruction set .............................................................................................. 627 a.1 instruction list........................................................................................................... ......... 627 a.2 instruction codes.......................................................................................................... ...... 651 a.3 operation code map ......................................................................................................... . 665 a.4 number of states required for instruction execution ....................................................... 669 a.5 bus states during instruction execution ............................................................................ 683 a.6 condition code modification............................................................................................. 697 xiii appendix b internal i/o register .................................................................................. 703 b.1 addresses.................................................................................................................. .......... 703 b.2 functions .................................................................................................................. .......... 709 appendix c i/o port block diagrams .......................................................................... 789 c.1 port 1 block diagrams ...................................................................................................... . 789 c.2 port 3 block diagrams ...................................................................................................... . 793 c.3 port 4 block diagram....................................................................................................... .. 797 c.4 port 7 block diagrams ...................................................................................................... . 798 c.5 port 9 block diagram....................................................................................................... .. 803 c.6 port a block diagrams ...................................................................................................... 804 c.7 port b block diagram ....................................................................................................... . 808 c.8 port c block diagram ....................................................................................................... . 809 c.9 port d block diagram....................................................................................................... . 810 c.10 port e block diagram ...................................................................................................... .. 811 c.11 port f block diagrams ..................................................................................................... .. 812 c.12 port g block diagrams ..................................................................................................... . 818 appendix d pin states ....................................................................................................... 822 d.1 port states in each processing state .................................................................................. 822 appendix e timing of transition to and recovery from hardware standby mode ................................................................. 825 appendix fproduct code lineup ................................................................................. 826 appendix g package dimensions .................................................................................. 827 xiv figures figure 1-1 h8s/2214 internal block diagram ...................................................................... 5 figure 1-2 h8s/2214 pin arrangement (tfp-100b, tfp-100g: top view) ....................... 6 figure 1-3 h8s/2214 pin arrangement (tbp-112: top view) ............................................ 7 figure 2-1 cpu operating modes ......................................................................................... 20 figure 2-2 exception vector table (normal mode) ............................................................. 21 figure 2-3 stack structure in normal mode ......................................................................... 22 figure 2-4 exception vector table (advanced mode) ......................................................... 23 figure 2-5 stack structure in advanced mode ..................................................................... 24 figure 2-6 memory map........................................................................................................ 25 figure 2-7 cpu registers...................................................................................................... 26 figure 2-8 usage of general registers.................................................................................. 27 figure 2-9 stack................................................................................................................ ..... 28 figure 2-10 general register data formats (1) ...................................................................... 31 figure 2-11 general register data formats (2) ...................................................................... 32 figure 2-12 memory data formats ......................................................................................... 33 figure 2-13 instruction formats (examples)........................................................................... 47 figure 2-14 branch address specification in memory indirect mode ................................... 51 figure 2-15 processing states.................................................................................................. 5 5 figure 2-16 state transitions................................................................................................... 56 figure 2-17 stack structure after exception handling (examples) ........................................ 59 figure 2-18 on-chip memory access cycle .......................................................................... 61 figure 2-19 pin states during on-chip memory access ........................................................ 62 figure 2-20 on-chip supporting module access cycle......................................................... 63 figure 2-21 pin states during on-chip supporting module access....................................... 64 figure 3-1 memory map in each operating mode in the h8s/2214.................................... 72 figure 4-1 exception sources................................................................................................ 74 figure 4-2 reset sequence (modes 2 and 3: not available in the h8s/2214) ...................... 78 figure 4-3 reset sequence (mode 4) .................................................................................... 79 figure 4-4 interrupt sources and number of interrupts ........................................................ 81 figure 4-5 stack status after exception handling (normal modes: not available in the h8s/2214) ................................................ 83 figure 4-6 stack status after exception handling (advanced modes)................................. 83 figure 4-7 operation when sp value is odd ........................................................................ 84 figure 5-1 block diagram of interrupt controller ................................................................ 86 figure 5-2 block diagram of interrupts irq7 to irq0 ........................................................ 93 figure 5-3 timing of setting irqnf ..................................................................................... 94 figure 5-4 block diagram of interrupt control operation.................................................... 98 figure 5-5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 ................................................................................................................. 101 figure 5-6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2 ................................................................................................................. 103 xv figure 5-7 interrupt exception handling .............................................................................. 104 figure 5-8 contention between interrupt generation and disabling .................................... 106 figure 5-9 interrupt control for dtc and dmac................................................................ 108 figure 6-1 block diagram of bus controller ........................................................................ 112 figure 6-2 overview of area divisions ................................................................................ 126 figure 6-3 csn signal output timing (n = 0 to 7)................................................................ 130 figure 6-4 access sizes and data alignment control (8-bit access space)........................ 131 figure 6-5 access sizes and data alignment control (16-bit access space)...................... 132 figure 6-6 bus timing for 8-bit 2-state access space ........................................................ 134 figure 6-7 bus timing for 8-bit 3-state access space ........................................................ 135 figure 6-8 bus timing for 16-bit 2-state access space (1) (even address byte access).. 136 figure 6-9 bus timing for 16-bit 2-state access space (2) (odd address byte access) ... 137 figure 6-10 bus timing for 16-bit 2-state access space (3) (word access)........................ 138 figure 6-11 bus timing for 16-bit 3-state access space (1) (even address byte access).. 139 figure 6-12 bus timing for 16-bit 3-state access space (2) (odd address byte access) ... 140 figure 6-13 bus timing for 16-bit 3-state access space (3) (word access)........................ 141 figure 6-14 example of wait state insertion timing ............................................................. 143 figure 6-15 example of burst rom access timing (when ast0 = brsts1 = 1).............. 145 figure 6-16 example of burst rom access timing (when ast0 = brsts1 = 0).............. 146 figure 6-17 example of idle cycle operation (1) ................................................................... 147 figure 6-18 example of idle cycle operation (2) ................................................................... 148 figure 6-19 relationship between chip select ( cs ) and read ( rd )...................................... 149 figure 6-20 bus-released state transition timing ................................................................ 153 figure 6-21 multichip block diagram .................................................................................... 156 figure 6-22 timing of external module area access by dtc .............................................. 162 figure 7-1 block diagram of dmac.................................................................................... 164 figure 7-2 areas for register re-setting by dtc (example: channel 0a) ......................... 192 figure 7-3 operation in sequential mode ............................................................................. 199 figure 7-4 example of sequential mode setting procedure.................................................. 200 figure 7-5 operation in idle mode........................................................................................ 202 figure 7-6 example of idle mode setting procedure............................................................ 203 figure 7-7 operation in repeat mode.................................................................................... 206 figure 7-8 example of repeat mode setting procedure ....................................................... 207 figure 7-9 operation in normal mode.................................................................................. 209 figure 7-10 example of normal mode setting procedure...................................................... 210 figure 7-11 operation in block transfer mode (blkdir = 0) ............................................. 212 figure 7-12 operation in block transfer mode (blkdir = 1) ............................................. 213 figure 7-13 operation flow in block transfer mode ............................................................. 215 figure 7-14 example of block transfer mode setting procedure .......................................... 216 figure 7-15 example of dma transfer bus timing .............................................................. 219 figure 7-16 example of short address mode transfer .......................................................... 220 figure 7-17 example of full address mode (cycle steal) transfer....................................... 221 figure 7-18 example of full address mode (burst mode) transfer...................................... 222 xvi figure 7-19 example of full address mode (block transfer mode) transfer ...................... 223 figure 7-20 example of dreq pin falling edge activated normal mode transfer............. 224 figure 7-21 example of dreq pin falling edge activated block transfer mode transfer. 225 figure 7-22 example of dreq level activated normal mode transfer .............................. 226 figure 7-23 example of dreq level activated block transfer mode transfer .................. 227 figure 7-24 example of multi-channel transfer.................................................................... 228 figure 7-25 example of procedure for continuing transfer on channel interrupted by nmi interrupt.................................................................................................. 230 figure 7-26 example of procedure for forcibly terminating dmac operation ................... 231 figure 7-27 example of procedure for clearing full address mode...................................... 232 figure 7-28 block diagram of transfer end/transfer break interrupt .................................. 233 figure 7-29 dmac register update timing.......................................................................... 234 figure 7-30 contention between dmac register update and cpu read ............................. 235 figure 8-1 block diagram of dtc........................................................................................ 238 figure 8-2 flowchart of dtc operation ............................................................................... 247 figure 8-3 block diagram of dtc activation source control ............................................ 249 figure 8-4 correspondence between dtc vector address and register information ......... 252 figure 8-5 location of register information in address space............................................ 253 figure 8-6 memory mapping in normal mode..................................................................... 254 figure 8-7 memory mapping in repeat mode...................................................................... 255 figure 8-8 memory mapping in block transfer mode ......................................................... 256 figure 8-9 chain transfer memory map .............................................................................. 257 figure 8-10 dtc operation timing (example in normal mode or repeat mode)................ 258 figure 8-11 dtc operation timing (example of block transfer mode, with block size of 2) .................................. 258 figure 8-12 dtc operation timing (example of chain transfer) ........................................ 259 figure 9-1 port 1 pin functions ............................................................................................. 269 figure 9-2 port 3 pin functions ............................................................................................. 280 figure 9-3 port 4 pin functions ............................................................................................. 287 figure 9-4 port 7 pin functions ............................................................................................. 291 figure 9-5 port 9 pin functions ............................................................................................. 297 figure 9-6 port a pin functions............................................................................................ 298 figure 9-7 port b pin functions ............................................................................................ 305 figure 9-8 port c pin functions ............................................................................................ 313 figure 9-9 port c pin functions (modes 4 and 5) ................................................................. 316 figure 9-10 port c pin functions (mode 6) ............................................................................ 317 figure 9-11 port c pin functions (mode 7) ............................................................................ 317 figure 9-12 port d pin functions............................................................................................ 319 figure 9-13 port d pin functions (modes 4 to 6) ................................................................... 322 figure 9-14 port d pin functions (mode 7)............................................................................ 323 figure 9-15 port e pin functions ............................................................................................ 324 figure 9-16 port e pin functions (modes 4 to 6).................................................................... 327 figure 9-17 port e pin functions (mode 7) ............................................................................ 328 xvii figure 9-18 port f pin functions ............................................................................................ 330 figure 9-19 port g pin functions............................................................................................ 335 figure 10-1 block diagram of h8s/2214 tpu ....................................................................... 345 figure 10-2 16-bit register access operation [bus master ? tcnt (16 bits)].................. 370 figure 10-3 8-bit register access operation [bus master ? tcr (upper 8 bits)].............. 370 figure 10-4 8-bit register access operation [bus master ? tmdr (lower 8 bits)].......... 371 figure 10-5 8-bit register access operation [bus master ? tcr and tmdr (16 bits)].... 371 figure 10-6 example of counter operation setting procedure............................................... 373 figure 10-7 free-running counter operation ........................................................................ 374 figure 10-8 periodic counter operation ................................................................................. 375 figure 10-9 example of setting procedure for waveform output by compare match ....... 375 figure 10-10 example of 0 output/1 output operation............................................................ 376 figure 10-11 example of toggle output operation.................................................................. 376 figure 10-12 example of input capture operation setting procedure...................................... 377 figure 10-13 example of input capture operation ................................................................... 378 figure 10-14 example of synchronous operation setting procedure....................................... 379 figure 10-15 example of synchronous operation .................................................................... 380 figure 10-16 compare match buffer operation ....................................................................... 381 figure 10-17 input capture buffer operation ........................................................................... 382 figure 10-18 example of buffer operation setting procedure ................................................. 382 figure 10-19 example of buffer operation (1) ......................................................................... 383 figure 10-20 example of buffer operation (2) ......................................................................... 384 figure 10-21 example of pwm mode setting procedure......................................................... 386 figure 10-22 example of pwm mode operation (1)................................................................ 387 figure 10-23 example of pwm mode operation (2)................................................................ 388 figure 10-24 example of pwm mode operation (3)................................................................ 389 figure 10-25 example of phase counting mode setting procedure ......................................... 390 figure 10-26 example of phase counting mode 1 operation .................................................. 391 figure 10-27 example of phase counting mode 2 operation .................................................. 392 figure 10-28 example of phase counting mode 3 operation .................................................. 393 figure 10-29 example of phase counting mode 4 operation .................................................. 394 figure 10-30 count timing in internal clock operation.......................................................... 397 figure 10-31 count timing in external clock operation ......................................................... 397 figure 10-32 output compare output timing.......................................................................... 398 figure 10-33 input capture input signal timing ...................................................................... 398 figure 10-34 counter clear timing (compare match)............................................................. 399 figure 10-35 counter clear timing (input capture) ................................................................ 399 figure 10-36 buffer operation timing (compare match)........................................................ 400 figure 10-37 buffer operation timing (input capture)............................................................ 400 figure 10-38 tgi interrupt timing (compare match).............................................................. 401 figure 10-39 tgi interrupt timing (input capture).................................................................. 402 figure 10-40 tciv interrupt setting timing ............................................................................ 403 figure 10-41 tciu interrupt setting timing ............................................................................ 403 xviii figure 10-42 timing for status flag clearing by cpu............................................................. 404 figure 10-43 timing for status flag clearing by dtc/dmac activation.............................. 404 figure 10-44 phase difference, overlap, and pulse width in phase counting mode .............. 405 figure 10-45 contention between tcnt write and clear operations ..................................... 406 figure 10-46 contention between tcnt write and increment operations.............................. 407 figure 10-47 contention between tgr write and compare match......................................... 408 figure 10-48 contention between buffer register write and compare match........................ 409 figure 10-49 contention between tgr read and input capture.............................................. 410 figure 10-50 contention between tgr write and input capture ............................................ 411 figure 10-51 contention between buffer register write and input capture............................ 412 figure 10-52 contention between overflow and counter clearing.......................................... 413 figure 10-53 contention between tcnt write and overflow ................................................. 414 figure 11-1 block diagram of wdt....................................................................................... 416 figure 11-2 format of data written to tcnt and tcsr (example of wdt0) .................... 422 figure 11-3 format of data written to rstcsr (example of wdt0).................................. 423 figure 11-4 operation in watchdog timer mode ................................................................... 424 figure 11-5 operation in interval timer mode ....................................................................... 425 figure 11-6 timing of ovf setting ........................................................................................ 426 figure 11-7 timing of wovf setting .................................................................................... 427 figure 11-8 contention between tcnt write and increment................................................ 428 figure 12-1 block diagram of sci0........................................................................................ 433 figure 12-2 block diagram of sci1 and sci2........................................................................ 434 figure 12-3 examples of base clock when average transfer rate is selected (1) ............... 461 figure 12-4 examples of base clock when average transfer rate is selected (2) ............... 462 figure 12-5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) .............................................. 468 figure 12-6 relation between output clock and transfer data phase (asynchronous mode).......................................................................................... 470 figure 12-7 sample sci initialization flowchart.................................................................... 471 figure 12-8 sample serial transmission flowchart................................................................ 472 figure 12-9 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) ................................................ 474 figure 12-10 sample serial reception data flowchart (1)....................................................... 475 figure 12-11 sample serial reception data flowchart (2)....................................................... 476 figure 12-12 example of sci operation in reception (example with 8-bit data, parity, one stop bit) ................................................ 478 figure 12-13 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) ........................................ 480 figure 12-14 sample multiprocessor serial transmission flowchart ...................................... 481 figure 12-15 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit)............................ 483 figure 12-16 sample multiprocessor serial reception flowchart (1)...................................... 484 figure 12-17 sample multiprocessor serial reception flowchart (2)...................................... 485 xix figure 12-18 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)............................ 486 figure 12-19 data format in synchronous communication..................................................... 487 figure 12-20 sample sci initialization flowchart.................................................................... 488 figure 12-21 sample serial transmission flowchart................................................................ 489 figure 12-22 example of sci operation in transmission ........................................................ 490 figure 12-23 sample serial reception flowchart ..................................................................... 492 figure 12-24 example of sci operation in reception.............................................................. 493 figure 12-25 sample flowchart of simultaneous serial transmit and receive operations .... 494 figure 12-26 receive data sampling timing in asynchronous mode .................................... 499 figure 12-27 example of clocked synchronous transmission by dtc .................................. 500 figure 12-28 sample flowchart for mode transition during transmission ............................. 501 figure 12-29 asynchronous transmission using internal clock ............................................. 502 figure 12-30 synchronous transmission using internal clock................................................ 502 figure 12-31 sample flowchart for mode transition during reception .................................. 503 figure 12-32 operation when switching from sck pin function to port pin function .......... 504 figure 12-33 operation when switching from sck pin function to port pin function (example of preventing low-level output) ....................................................... 505 figure 13-1 block diagram of d/a converter........................................................................ 508 figure 13-2 example of d/a converter operation ................................................................. 512 figure 14-1 block diagram of ram....................................................................................... 513 figure 15-1 block diagram of rom....................................................................................... 517 figure 15-2 block diagram of flash memory ........................................................................ 521 figure 15-3 flash memory state transitions .......................................................................... 522 figure 15-4 boot mode........................................................................................................... . 523 figure 15-5 user program mode ............................................................................................. 524 figure 15-6 reading overlap ram data in user mode or user program mode................... 525 figure 15-7 writing overlap ram data in user program mode ........................................... 526 figure 15-8 flash memory blocks .......................................................................................... 527 figure 15-9 system configuration in boot mode ................................................................... 539 figure 15-10 boot mode execution procedure ......................................................................... 540 figure 15-11 automatic sci bit rate adjustment.................................................................... 541 figure 15-12 ram areas in boot mode ................................................................................... 542 figure 15-13 user program mode execution procedure .......................................................... 544 figure 15-14 program/program-verify flowchart.................................................................... 547 figure 15-15 erase/erase-verify flowchart.............................................................................. 549 figure 15-16 flash memory state transitions .......................................................................... 553 figure 15-17 flowchart for flash memory emulation in ram ............................................... 554 figure 15-18 example of ram overlap operation .................................................................. 555 figure 15-19 on-chip rom memory map .............................................................................. 557 figure 15-20 socket adapter pin correspondence diagram .................................................... 558 figure 15-21 timing waveforms for memory read after memory write ............................... 561 xx figure 15-22 timing waveforms in transition from memory read mode to another mode .................................................................................................. 562 figure 15-23 ce and oe enable state read timing waveforms ............................................. 562 figure 15-24 ce and oe clock system read timing waveforms........................................... 563 figure 15-25 auto-program mode timing waveforms............................................................ 564 figure 15-26 auto-erase mode timing waveforms................................................................. 566 figure 15-27 status read mode timing waveforms................................................................ 567 figure 15-28 oscillation stabilization time, boot program transfer time, and power-downsequence ................................................................................. 569 figure 15-29 power-on/off timing (boot mode).................................................................... 573 figure 15-30 power-on/off timing (user program mode)...................................................... 574 figure 15-31 mode transition timing (example: boot mode user mode ? user program mode).......................... 575 figure 16-1 block diagram of clock pulse generator............................................................ 577 figure 16-2 connection of crystal resonator (example) ....................................................... 581 figure 16-3 crystal resonator equivalent circuit .................................................................. 581 figure 16-4 example of incorrect board design .................................................................... 582 figure 16-5 external clock input (examples)......................................................................... 583 figure 16-6 external clock input timing ............................................................................... 584 figure 16-7 example of external clock switching circuit..................................................... 585 figure 16-8 example of external clock switchover timing.................................................. 585 figure 17-1 mode transitions ................................................................................................. 589 figure 17-2 medium-speed mode transition and clearance timing..................................... 595 figure 17-3 software standby mode application example.................................................... 600 figure 17-4 hardware standby mode timing (example)....................................................... 601 figure 18-1 power supply voltage and operating ranges ..................................................... 604 figure 18-2 output load circuit ............................................................................................. 609 figure 18-3 system clock timing .......................................................................................... 610 figure 18-4 oscillator settling timing.................................................................................... 611 figure 18-5 reset input timing .............................................................................................. 612 figure 18-6 interrupt input timing ......................................................................................... 612 figure 18-7 basic bus timing (two-state access) ................................................................ 615 figure 18-8 basic bus timing (three-state access) .............................................................. 616 figure 18-9 basic bus timing (three-state access with one wait state) ............................ 617 figure 18-10 burst rom access timing (two-state access) ................................................. 618 figure 18-11 external bus release timing............................................................................... 619 figure 18-12 i/o port input/output timing .............................................................................. 621 figure 18-13 tpu input/output timing.................................................................................... 621 figure 18-14 tpu clock input timing ..................................................................................... 621 figure 18-15 sck clock input timing ..................................................................................... 622 figure 18-16 sci input/output timing (clock synchronous mode)........................................ 622 figure 18-17 dmac tend output timing ............................................................................. 623 figure 18-18 dmac dreq output timing ............................................................................. 623 xxi figure a-1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states) ................................................ 684 figure c-1 port 1 block diagram (pins p10 and p11)........................................................... 789 figure c-2 port 1 block diagram (pins p12 and p13)........................................................... 790 figure c-3 port 1 block diagram (pins p14 and p16)........................................................... 791 figure c-4 port 1 block diagram (pins p15 and p17)........................................................... 792 figure c-5 port 3 block diagram (pins p30 and p33)........................................................... 793 figure c-6 port 3 block diagram (pins p31 and p34)........................................................... 794 figure c-7 port 3 block diagram (pins p32 and p35)........................................................... 795 figure c-8 port 3 block diagram (pin p36) .......................................................................... 796 figure c-9 port 4 block diagram (pins p40 to p44, p46, and p47) ...................................... 797 figure c-10 port 4 block diagram (pin p45) .......................................................................... 797 figure c-11 port 7 block diagram (pins p70 and p71)........................................................... 798 figure c-12 port 7 block diagram (pins p72 and p73)........................................................... 799 figure c-13 port 7 block diagram (pin p74) .......................................................................... 800 figure c-14 port 7 block diagram (pins p75 and p76)........................................................... 801 figure c-15 port 7 block diagram (pin p77) .......................................................................... 802 figure c-16 port 9 block diagram (pin p96) .......................................................................... 803 figure c-17 port a block diagram (pin pa0) ........................................................................ 804 figure c-18 port a block diagram (pin pa1) ........................................................................ 805 figure c-19 port a block diagram (pin pa2) ........................................................................ 806 figure c-20 port a block diagram (pin pa3) ........................................................................ 807 figure c-21 port b block diagram (pins pb0 to pb7) ........................................................... 808 figure c-22 port c block diagram (pins pc0 to pc7) ........................................................... 809 figure c-23 port d block diagram (pins pd0 to pd7)........................................................... 810 figure c-24 port e block diagram (pins pe0 to pe7)............................................................ 811 figure c-25 port f block diagram (pin pf0).......................................................................... 812 figure c-26 port f block diagram (pin pf1).......................................................................... 813 figure c-27 port f block diagram (pin pf2).......................................................................... 814 figure c-28 port f block diagram (pin pf3).......................................................................... 815 figure c-29 port f block diagram (pins pf4 to pf6)............................................................. 816 figure c-30 port f block diagram (pin pf7).......................................................................... 817 figure c-31 port g block diagram (pin pg0) ........................................................................ 818 figure c-32 port g block diagram (pin pg1) ........................................................................ 819 figure c-33 port g block diagram (pins pg2 and pg3)........................................................ 820 figure c-34 port g block diagram (pin pg4) ........................................................................ 821 figure e-1 timing of transition to hardware standby mode............................................... 825 figure e-2 timing of recovery from hardware standby mode ........................................... 825 figure g-1 tfp-100b package dimensions .......................................................................... 827 figure g-2 tfp-100g package dimensions .......................................................................... 828 figure g-3 tbp-112 package dimensions ............................................................................ 829 xxii tables table 1-1 overview............................................................................................................. .2 table 1-2 pin functions in each operating mode ............................................................... 8 table 1-3 pin functions........................................................................................................ 12 table 2-1 instruction classification ..................................................................................... 34 table 2-2 combinations of instructions and addressing modes ......................................... 35 table 2-3 instructions classified by function...................................................................... 38 table 2-4 addressing modes................................................................................................ 48 table 2-5 absolute address access ranges........................................................................ 50 table 2-6 effective address calculation ............................................................................. 52 table 2-7 exception handling types and priority............................................................... 57 table 3-1 mcu operating mode selection ......................................................................... 65 table 3-2 mcu registers..................................................................................................... 66 table 3-3 relationship between res and mres pin values and type of reset................ 68 table 3-3 pin functions in each mode ................................................................................ 71 table 4-1 exception handling types and priority............................................................... 73 table 4-2 exception vector table ....................................................................................... 75 table 4-3 reset types.......................................................................................................... 76 table 4-4 status of ccr and exr after trace exception handling ................................... 80 table 4-5 status of ccr and exr after trap instruction exception handling .................. 82 table 5-1 interrupt controller pins ...................................................................................... 87 table 5-2 interrupt controller registers .............................................................................. 87 table 5-3 correspondence between interrupt sources and ipr settings............................. 89 table 5-4 interrupt sources, vector addresses, and interrupt priorities ............................. 95 table 5-5 interrupt control modes ...................................................................................... 97 table 5-6 interrupts selected in each interrupt control mode (1) ...................................... 98 table 5-7 interrupts selected in each interrupt control mode (2) ...................................... 99 table 5-8 operations and control signal functions in each interrupt control mode ........ 99 table 5-9 interrupt response times .................................................................................... 105 table 5-10 number of states in interrupt handling routine execution statuses.................. 105 table 5-11 interrupt source selection and clearing control ................................................. 110 table 6-1 bus controller pins .............................................................................................. 113 table 6-2 bus controller registers ...................................................................................... 114 table 6-3 bus specifications for each area (basic bus interface) ..................................... 128 table 6-4 data buses used and valid strobes..................................................................... 133 table 6-5 pin states in idle cycle ........................................................................................ 150 table 6-6 pin states in bus released state.......................................................................... 152 table 6-7 external module expansion function pins.......................................................... 157 table 6-8 bus controller registers ...................................................................................... 157 table 7-1 overview of dmac functions (short address mode) ....................................... 165 table 7-2 overview of dmac functions (full address mode) ......................................... 166 table 7-3 dmac pins.......................................................................................................... 16 7 xxiii table 7-4 dmac registers.................................................................................................. 168 table 7-5 short address mode and full address mode (for 1 channel: example of channel 0) .............................................................. 169 table 7-6 dmac transfer modes ....................................................................................... 196 table 7-7 register functions in sequential mode ............................................................... 198 table 7-8 register functions in idle mode.......................................................................... 201 table 7-9 register functions in repeat mode ..................................................................... 204 table 7-10 register functions in normal mode.................................................................... 208 table 7-11 register functions in block transfer mode........................................................ 211 table 7-12 dmac activation sources .................................................................................. 217 table 7-13 dmac channel priority order............................................................................ 228 table 7-14 interrupt source priority order............................................................................ 233 table 8-1 dtc registers...................................................................................................... 23 9 table 8-2 dtc functions ..................................................................................................... 248 table 8-3 activation source and dtcer clearance........................................................... 249 table 8-4 interrupt sources, dtc vector addresses, and corresponding dtces ............. 251 table 8-5 register information in normal mode ................................................................ 254 table 8-6 register information in repeat mode.................................................................. 255 table 8-7 register information in block transfer mode..................................................... 256 table 8-8 dtc execution statuses ...................................................................................... 259 table 8-9 number of states required for each execution status ....................................... 260 table 9-1 h8s/2214 port functions ..................................................................................... 266 table 9-2 port 1 registers .................................................................................................... 2 70 table 9-3 port 1 pin functions ............................................................................................. 272 table 9-4 port 3 registers .................................................................................................... 2 80 table 9-5 port 3 pin functions ............................................................................................. 285 table 9-6 port 4 registers .................................................................................................... 2 87 table 9-7 port 7 registers .................................................................................................... 2 92 table 9-8 port 7 pin functions ............................................................................................. 295 table 9-9 port 9 registers.................................................................................................... 2 97 table 9-10 port a registers ................................................................................................... 2 99 table 9-11 port a pin functions............................................................................................ 302 table 9-12 mos input pull-up states (port a) ..................................................................... 304 table 9-13 port b registers ................................................................................................... 3 06 table 9-14 port b pin functions ............................................................................................ 308 table 9-15 mos input pull-up states (port b) ..................................................................... 312 table 9-16 port c registers ................................................................................................... 3 14 table 9-17 mos input pull-up states (port c) ..................................................................... 318 table 9-18 port d registers ................................................................................................... 3 20 table 9-19 mos input pull-up states (port d) ..................................................................... 323 table 9-20 port e registers.................................................................................................... 325 table 9-21 mos input pull-up states (port e)...................................................................... 329 table 9-22 port f registers.................................................................................................... 331 xxiv table 9-23 port f pin functions ............................................................................................ 333 table 9-24 port g registers ................................................................................................... 3 36 table 9-25 port g pin functions............................................................................................ 338 table 10-1 tpu functions ..................................................................................................... 34 3 table 10-2 tpu pins ............................................................................................................ .. 346 table 10-3 tpu registers ...................................................................................................... 3 47 table 10-4 tpu clock sources.............................................................................................. 350 table 10-5 register combinations in buffer operation ........................................................ 381 table 10-6 pwm output registers and output pins ............................................................. 386 table 10-7 phase counting mode clock input pins .............................................................. 390 table 10-8 up/down-count conditions in phase counting mode 1 .................................... 391 table 10-9 up/down-count conditions in phase counting mode 2 .................................... 392 table 10-10 up/down-count conditions in phase counting mode 3 .................................... 393 table 10-11 up/down-count conditions in phase counting mode 4 .................................... 394 table 10-12 interrupt sources and dma controller (dmac) and data transfer (dtc) activation ................................................................... 395 table 11-1 wdt registers..................................................................................................... 41 7 table 12-1 sci pins............................................................................................................ .... 435 table 12-2 sci registers....................................................................................................... . 436 table 12-3 brr settings for various bit rates (asynchronous mode)................................ 450 table 12-4 brr settings for various bit rates (clocked synchronous mode) ................... 453 table 12-5 maximum bit rate for each frequency (asynchronous mode) ......................... 455 table 12-6 maximum bit rate with external clock input (asynchronous mode) ............... 456 table 12-7 maximum bit rate with external clock input (clocked synchronous mode) ... 456 table 12-8 smr settings and serial transfer format selection ........................................... 465 table 12-9 smr and scr settings and sci clock source selection ................................... 465 table 12-10 smr0, scr0, semr0 settings and sci c l ock s ource select i on (s ci0 onl y) .. 466 table 12-11 serial transfer formats (asynchronous mode) .................................................. 469 table 12-12 receive errors and conditions for occurrence ................................................... 478 table 12-13 sci interrupt sources........................................................................................... 496 table 12-14 state of ssr status flags and transfer of receive data..................................... 497 table 13-1 pin configuration ................................................................................................. 50 9 table 13-2 d/a converter registers...................................................................................... 509 table 14-1 ram register ...................................................................................................... 51 4 table 15-1 rom register ...................................................................................................... 51 8 table 15-2 operating modes and rom area (f-ztat version and mask rom version) .. 519 table 15-3 differences between boot mode and user program mode ................................. 526 table 15-4 pin configuration ................................................................................................. 52 8 table 15-5 register configuration ......................................................................................... 529 table 15-6 flash memory erase blocks ................................................................................ 535 table 15-7 flash memory area divisions ............................................................................. 536 table 15-8 setting on-board programming modes .............................................................. 538 xxv table 15-9 system clock frequencies for which automatic adjustment of h8s/2214 bit rate is possible ............................................................................. 541 table 15-10 hardware protection ............................................................................................ 550 table 15-11 software protection.............................................................................................. 55 1 table 15-12 programmer mode pin settings ........................................................................... 557 table 15-13 settings for various operating modes in programmer mode ............................. 559 table 15-14 programmer mode commands ............................................................................ 560 table 15-15 ac characteristics in transition to memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c)........................... 560 table 15-16 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c)........................... 561 table 15-17 ac characteristics in memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c)........................... 562 table 15-18 ac characteristics in auto-program mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) ........................... 564 table 15-19 ac characteristics in auto-erase mode (conditions: v cc = 3.3 v 3.0 v, v ss = 0 v, t a = 25c 5c)........................... 565 table 15-20 ac characteristics in status read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c)........................... 567 table 15-21 status read mode return commands ................................................................. 568 table 15-22 status polling output truth table ....................................................................... 568 table 15-23 stipulated transition times to command wait state ......................................... 568 table 15-24 flash memory operating states........................................................................... 570 table 15-25 registers present in f-ztat version but absent in mask rom version ......... 576 table 16-1 clock pulse generator register ........................................................................... 578 table 16-2 damping resistance value .................................................................................. 581 table 16-3 crystal resonator parameters .............................................................................. 582 table 16-4 external clock input conditions.......................................................................... 584 table 16-5 external clock input conditions when the duty adjustment circuit is not used............................................................................................................ 584 table 17-1 h8s/2214 internal states in each mode.............................................................. 588 table 17-2 power-down mode registers .............................................................................. 590 table 17-3 mstp bits and corresponding on-chip supporting modules............................ 597 table 17-4 oscillation stabilization time settings................................................................ 599 table 17-5 ? pin state in each processing mode .................................................................. 602 table 18-1 absolute maximum ratings ................................................................................ 603 table 18-2 dc characteristics (1).......................................................................................... 605 table 18-3 dc characteristics (2).......................................................................................... 607 table 18-4 dc characteristics (3).......................................................................................... 608 table 18-5 permissible output currents ................................................................................ 609 table 18-6 clock timing ....................................................................................................... 6 10 table 18-7 control signal timing ......................................................................................... 611 table 18-8 bus timing .......................................................................................................... 613 xxvi table 18-9 timing of on-chip supporting modules............................................................. 620 table 18-10 dmac timing ..................................................................................................... 623 table 18-11 d/a conversion characteristics .......................................................................... 624 table 18-12 flash memory characteristics ............................................................................. 625 table a-1 data transfer instructions.................................................................................... 629 table a-2 arithmetic instructions ........................................................................................ 632 table a-3 logical instructions.............................................................................................. 636 table a-4 shift instructions.................................................................................................. 6 37 table a-5 bit-manipulation instructions.............................................................................. 640 table a-6 branch instructions .............................................................................................. 645 table a-7 system control instructions................................................................................. 648 table a-8 block transfer instructions.................................................................................. 650 table a-9 instruction codes ................................................................................................. 651 table a-10 operation code map (1) ...................................................................................... 665 table a-11 operation code map (2) ...................................................................................... 666 table a-12 operation code map (3) ...................................................................................... 667 table a-13 operation code map (4) ...................................................................................... 668 table a-14 number of states per cycle ................................................................................. 670 table a-15 number of cycles in instruction execution......................................................... 671 table a-16 instruction execution cycles ............................................................................... 685 table a-17 condition code modification .............................................................................. 698 table d-1 i/o port states in each processing state.............................................................. 822 table f-1 h8s/2214 product code lineup .......................................................................... 826 1 section 1 overview 1.1 overview the h8s/2214 is a microcomputer (mcu: microcomputer unit), built around the h8s/2000 cpu, employing hitachi's proprietary architecture, and equipped with the on-chip peripheral functions necessary for system configuration. the h8s/2000 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include dma controller (dmac) data transfer controller (dtc) bus masters, rom and ram memory, a16-bit timer-pulse unit (tpu), watchdog timer (wdt), serial communication interface (sci), d/a converter, and i/o ports. the on-chip rom is either flash memory (f-ztat?*) or mask rom, with a capacity of 128 kbytes. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. the features of the h8s/2214 are shown in table 1-1. note: * f-ztat? is a trademark of hitachi, ltd. 2 table 1-1 overview item specification cpu ? general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? high-speed operation suitable for realtime control ? maximum clock rate 16 mhz ? high-speed arithmetic operations (at 16 mhz operation) 8/16/32-bit register-register add/subtract : 62.5 ns 16 16-bit register-register multiply : 1250 ns 32 16-bit register-register divide : 1250 ns ? instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit move/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions ? two cpu operating modes ? normal mode : 64-kbyte address space (not available in the h8s/2214) ? advanced mode : 16-mbyte address space bus controller ? address space divided into 8 areas, with bus specifications settable independently for each area ? chip select output possible for each area ? choice of 8-bit or 16-bit access space for each area ? 2-state or 3-state access space can be designated for each area ? number of program wait states can be set for each area ? burst rom directly connectable ? external bus release function dma controller (dmac) ? choice of short address mode or full address mode ? four channels in short address mode two channels in full address mode ? transfer possible in repeat mode, block transfer mode, etc. ? can be activated by internal interrupt 3 item specification data transfer controller (dtc) ? can be activated by internal interrupt or software ? multiple transfers or multiple types of transfer possible for one activation source ? transfer possible in repeat mode, block transfer mode, etc. ? request can be sent to cpu for interrupt that activated dtc 16-bit timer-pulse unit (tpu) ? 3-channel 16-bit timer on-chip ? pulse i/o processing capability for up to 8 pins ? automatic 2-phase encoder count capability watchdog timer (wdt) 1 channel ? watchdog timer or interval timer selectable serial communication interface (sci) 3 channels (sci0 to sci2) ? asynchronous mode or synchronous mode selectable ? multiprocessor communication function d/a converter ? resolution: 8 bits ? output: 1 channel i/o ports ? 72 i/o pins, 9 input-only pins memory ? flash memory or mask rom ? high-speed static ram product name rom ram h8s/2214 128 kbytes 12 kbytes interrupt controller ? nine external interrupt pins (nmi, irq0 to irq7 ) eight external expansion interrupt pins (exirq7 to exirq0) ? 31 internal interrupt sources ? eight priority levels settable power-down state ? medium-speed mode ? sleep mode ? module stop mode ? software standby mode ? hardware standby mode 4 item specification operating modes four mcu operating modes external data bus mode cpu operating mode description on-chip rom initial value maximum value 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled clock pulse generator clock pulse generators ? system clock pulse generator: 2 to 16 mhz built-in duty correction circuit packages ? 100-pin plastic tqfp (tfp-100b) ? 100-pin plastic tqfp (tfp-100g) ? 112-pin plastic tfbga (tbp-112) product lineup model name mask rom version z-tat? version rom/ram (bytes) packages hd6432214 hd64f2214 128 k/12 k tfp-100b, tfp-100g, tbp-112 5 1.2 internal block diagrams figures 1-1 shows internal block diagram of the h8s/2214. pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d v cc v cc v ss v ss reserve b pa3 / a19/sck2 pa2 / a18/rxd2 pa1 / a17/txd2 pa0 / a16 pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2/a10 pb1/a9 pb0/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p36 / exirq7 p35 / sck1/ irq5 p34 / rxd1 p33 / txd1 p32 / sck0/ irq4 p31 / rxd0 p30 / txd0 p40 / exirq0 p41 / exirq1 p42 / exirq2 p43 / exirq3 p44 / exirq4 p45 p46 / exirq5 p47 / exirq6 p10 / tioca0 /a20 p11 / tiocb0 /a21 p12 / tiocc0 / tclka/a22 p13 / tiocd0 / tclkb/a23 p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2/ tclkd p70 / dreq0 / cs4 p71 / dreq1 / cs5 p72 / tend0 / cs6 p73 / tend1 / cs7 p74 / mres / exdtce p75 / exms p76 / exmstp p77 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3 / irq7 pg0 / irq6 pf7/? pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / irq3 pf2 / wait pf1 / back pf0 / breq / irq2 sci1, 2 (2 channels) sci0 (1 channel, high speed uart) md2 md1 md0 extal xtal stby res nmi fwe h8s/2000 cpu dtc dmac wdt0 interrupt controller port e port 4 port 9 port 1 port 7 internal address bus system clock pulse generator port a port b bus controller port c port 3 port g port f rom (128 kb) ram (12 kb) internal data bus tpu (3 channels) peripheral data bus peripheral address bus d/a converter (1 channel) p96/da0 reserve avcc vref avss figure 1-1 h8s/2214 internal block diagram 6 1.3 pin description 1.3.1 pin arrangements figures 1-2 and 1-3 show the pin arrangements of the h8s/2214. p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36/ exirq7 p77 p76/exmstp p75/ exms p74/ mres / exdtce p73/ tend1 / cs7 p72/ tend0 / cs6 p71/ dreq1 / cs5 p70/ dreq0 / cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 pe2/d2 pe3/d3 pe4/d4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pf0/ breq / irq 2 pf1/ back pf2/ wait pf3/ lwr / irq3 pf4/ hwr pf5/ rd pf6/ as pf7/? md2 fwe extal vss xtal vcc stby nmi res vss reserve md1 md0 avcc vref p40/ exirq0 p41/ exirq1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p42/ exirq2 p43/ exirq3 p44/ exirq4 p45 p46/ exirq5 p47/ exirq6 p96/da0 reserve p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 pb7/a15 pb6/a14 pb5/a13 pb4/a12 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8 pb2/a10 pb3/a11 vcc pc0/a0 vss pb1/a9 tfp-100b tfp-100g (top view) figure 1-2 h8s/2214 pin arrangement (tfp-100b, tfp-100g: top view) 7 tbp-112 (top view) 1 2 3 4 5 6 7 8 9 10 11 a b c d e f g h j k pe4 pe1 pg3 pg0 p72 p75 p36 p33 p30 pe6 pe5 pe3 pe0 pg1 p71 p74 p35 p32 pf1 pd1 pd0 pe2 pg2 p73 p76 p34 pf0 pf2 pf4 pd4 pd3 pd2 pe7 pg4 p70 p77 p31 pf3 pf5 pf7 pd7 vcc pd6 pd5 pf6 md2 fwe extal pc0 vss vcc vss vss vcc vss xtal pc1 pc2 pc3 pc5 res nmi vcc stby pc4 pc6 pb0 pb6 p10 p17 p47 vref md1 vss pc7 pb1 pb3 pa1 p11 p14 p44 avcc md0 pb2 pb4 pb7 pa2 p13 p16 avss p46 p43 p41 p40 pb5 pa0 pa3 p12 p15 avss p96 p45 p42 l reserve reserve reserve reserve reserve reserve reserve reserve reserve figure 1-3 h8s/2214 pin arrangement (tbp-112: top view) 8 1.3.2 pin functions in each operating mode table 1-2 shows the pin functions of the h8s/2214 in each of the operating modes. table 1-2 pin functions in each operating mode pin no. pin name tfp-100b, tfp-100g tbp-112 mode 4 mode 5 mode 6 mode 7 prom mode 1 b2 pe5/d5 pe5/d5 pe5/d5 pe5 nc 2 b1 pe6/d6 pe6/d6 pe6/d6 pe6 nc 3 d4 pe7/d7 pe7/d7 pe7/d7 pe7 nc 4c2d8d8d8pd0d0 5c1d9d9d9pd1d1 6 d3 d10 d10 d10 pd2 d2 7 d2 d11 d11 d11 pd3 d3 8 d1 d12 d12 d12 pd4 d4 9 e4 d13 d13 d13 pd5 d5 10 e3 d14 d14 d14 pd6 d6 11 e1 d15 d15 d15 pd7 d7 12 e2, f3 vcc vcc vcc vcc vcc 13 f1 a0 a0 pc0/a0 pc0 a0 14 f2, f4 vss vss vss vss vss 15 g1 a1 a1 pc1/a1 pc1 a1 16 g2 a2 a2 pc2/a2 pc2 a2 17 g3 a3 a3 pc3/a3 pc3 a3 18 h1 a4 a4 pc4/a4 pc4 a4 19 g4 a5 a5 pc5/a5 pc5 a5 20 h2 a6 a6 pc6/a6 pc6 a6 21 j1 a7 a7 pc7/a7 pc7 a7 22 h3 pb0/a8 pb0/a8 pb0/a8 pb0 a8 23 j2 pb1/a9 pb1/a9 pb1/a9 pb1 oe 24 k1 pb2/a10 pb2/a10 pb2/a10 pb2 a10 25 j3 pb3/a11 pb3/a11 pb3/a11 pb3 a11 26 k2 pb4/a12 pb4/a12 pb4/a12 pb4 a12 27 l2 pb5/a13 pb5/a13 pb5/a13 pb5 a13 28 h4 pb6/a14 pb6/a14 pb6/a14 pb6 a14 9 pin no. pin name tfp-100b, tfp-100g tbp-112 mode 4 mode 5 mode 6 mode 7 prom mode 29 k3 pb7/a15 pb7/a15 pb7/a15 pb7 a15 30 l3 pa0/a16 pa0/a16 pa0/a16 pa0 a16 31 j4 pa1/a17/txd2 pa1/a17/txd2 pa1/a17/txd2 pa1/txd2 vcc 32 k4 pa2/a18/rxd2 pa2/a18/rxd2 pa2/a18/rxd2 pa2/rxd2 vcc 33 l4 pa3/a19/sck2 pa3/a19/sck2 pa3/a19/sck2 pa3/sck2 nc 34 h5 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0 nc 35 j5 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0 nc 36 l5 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka nc 37 k5 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb nc 38 j6 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 nc 39 l6 p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc nc 40 k6 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 nc 41 h6 p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd nc 42 k7, l7 avss avss avss avss vss 43 j7 reserve reserve reserve reserve nc 44 l8 p96/da0 p96/da0 p96/da0 p96/da0 nc 45 h7 p47/ exirq6 p47/ exirq6 p47/ exirq6 p47/ exirq6 nc 46 k8 p46/ exirq5 p46/ exirq5 p46/ exirq5 p46/ exirq5 nc 47 l9 p45 p45 p45 p45 nc 48 j8 p44/ exirq4 p44/ exirq4 p44/ exirq4 p44/ exirq4 nc 49 k9 p43/ exirq3 p43/ exirq3 p43/ exirq3 p43/ exirq3 nc 50 l10 p42/ exirq2 p42/ exirq2 p42/ exirq2 p42/ exirq2 nc 51 k10 p41/ exirq1 p41/ exirq1 p41/ exirq1 p41/ exirq1 nc 52 k11 p40/ exirq0 p40/ exirq0 p40/ exirq0 p40/ exirq0 nc 53 h8 vref vref vref vref vcc 54 j10 avcc avcc avcc avcc vcc 55 j11 md0 md0 md0 md0 vss 10 pin no. pin name tfp-100b, tfp-100g tbp-112 mode 4 mode 5 mode 6 mode 7 prom mode 56 h9 md1 md1 md1 md1 vss 57 h10 reserve reserve reserve reserve nc 58 h11 vss vss vss vss nc 59 g8 res res res res vpp 60 g9 nmi nmi nmi nmi a9 61 g11 stby stby stby stby vss 62 f9, g10 vcc vcc vcc vcc vcc 63 f11 xtal xtal xtal xtal nc 64 f8, f10 vss vss vss vss vss 65 e11 extal extal extal extal nc 66 e10 fwe fwe fwe fwe fwe 67 e9 md2 md2 md2 md2 vss 68 d11 pf7/? pf7/? pf7/? pf7/? nc 69 e8 as as as pf6 nc 70 d10 rd rd rd pf5 nc 71 c11 hwr hwr hwr pf4 nc 72 d9 pf3/ lwr / irq3 pf3/ lwr / irq3 pf3/ lwr / irq3 pf3/ irq3 nc 73 c10 pf2/ wait pf2/ wait pf2/ wait pf2 ce 74 b11 pf1/ back pf1/ back pf1/ back pf1 pgm 75 c9 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ irq2 nc 76 a10 p30/txd0 p30/txd0 p30/txd0 p30/txd0 nc 77 d8 p31/rxd1 p31/rxd1 p31/rxd1 p31/rxd1 nc 78 b9 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 nc 79 a9 p33/txd1 p33/txd1 p33/txd1 p33/txd1 nc 80 c8 p34/rxd1 p34/rxd1 p34/rxd1 p34/rxd1 nc 81 b8 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 nc 82 a8 p36/ exirq7 p36/ exirq7 p36/ exirq7 p36/ exirq7 nc 83 d7 p77 p77 p77 p77 nc 84 c7 p76/exmstp p76/exmstp p76/exmstp p76/exmstp nc 85 a7 p75/ exms p75/ exms p75/ exms p75/ exms nc 11 pin no. pin name tfp-100b, tfp-100g tbp-112 mode 4 mode 5 mode 6 mode 7 prom mode 86 b7 p74/ mres / exdtce p74/ mres/ exdtce p74/ mres/ exdtce p74/ mres/ exdtce nc 87 c6 p73/ tend1 / cs7 p73/ tend1 / cs7 p73/ tend1 / cs7 p73/ tend1 nc 88 a6 p72/ tend0 / cs6 p72/ tend0 / cs6 p72/ tend0 / cs6 p72/ tend0 nc 89 b6 p71/ dreq1 / cs5 p71/ dreq1 / cs5 p71/ dreq1 / cs5 p71/ dreq1 nc 90 d6 p70/ dreq0 / cs4 p70/ dreq0 / cs4 p70/ dreq0 / cs4 p70/ dreq0 nc 91 a5 pg0/ irq6 pg0/ irq6 pg0/ irq6 pg0/ irq6 nc 92 b5 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ irq7 nc 93 c5 pg2/ cs2 pg2/ cs2 pg2/ cs2 pg2 nc 94 a4 pg3/ cs1 pg3/ cs1 pg3/ cs1 pg3 nc 95 d5 pg4/ cs0 pg4/ cs0 pg4/ cs0 pg4 nc 96 b4 pe0/d0 pe0/d0 pe0/d0 pe0 nc 97 a3 pe1/d1 pe1/d1 pe1/d1 pe1 nc 98 c4 pe2/d2 pe2/d2 pe2/d2 pe2 nc 99 b3 pe3/d3 pe3/d3 pe3/d3 pe3 nc 100 a2 pe4/d4 pe4/d4 pe4/d4 pe4 vss a1, a11, b10, c3, j9, l1, l11 reserve reserve reserve reserve reserve 12 1.3.3 pin functions table 1-3 outlines the pin functions of the h8s/2214. table 1-3 pin functions type symbol i/o name and function power vcc input power supply: for connection to the power supply. all v cc pins should be connected to the system power supply. vss input ground: for connection to ground (0 v). all v ss pins should be connected to the system power supply (0 v). clock xtal input crystal: connects to a crystal oscillator. see section 16, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal input external clock: connects to a crystal oscillator. the extal pin can also input an external clock. see section 16, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. ? output system clock: supplies the system clock to an external device. operating mode control md2 to md0 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the h8s/2214 is operating. except when the mode is changed, the mode pins (md2 to md0) must be pulled down or pulled up to a fixed level until powering off. md2 md1 md0 operating mode 000 1 10 1 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res input reset input: when this pin is driven low, the chip enters the power-on reset state. mres input manual reset: when this pin is driven low, the chip enters the manual reset state. 13 type symbol i/o name and function system control stby input standby: when this pin is driven low, a transition is made to hardware standby mode. breq input bus request: used by an external bus master to issue a bus request to the h8s/2214. back output bus request acknowledge: indicates that the bus has been released to an external bus master. fwe input flash write enable enables/disables flash memory programming. interrupts nmi input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq7 to irq0 input interrupt request 7 to 0: these pins request a maskable interrupt. address bus a23 to a0 output address bus: these pins output an address. data bus d15 to d0 i/o data bus: these pins constitute a bidirectional data bus. bus control cs7 to cs0 output chip select: signals for selecting areas 7 to 0. as output address strobe: when this pin is low, it indicates that address output on the address bus is enabled. rd output read: when this pin is low, it indicates that the external address space can be read. hwr output high write: a strobe signal that writes to external space and indicates that the upper half (d15 to d8) of the data bus is enabled. lwr output low write: a strobe signal that writes to external space and indicates that the lower half (d7 to d0) of the data bus is enabled. wait input wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space. external expansion exirq7 to exirq0 input external expansion interrupt request 7 to 0: input pins for interrupt requests from external modules. exms output external expansion module select: select signal for external modules. exdtc output external expansion dtc transfer end: dtc data transfer end signal for exirq7 to exirq0 input. exmstp output external expansion module stop: module stop signal for external modules. 14 type symbol i/o name and function dma controller (dmac) dreq1 , dreq0 input dma request 1 and 0: these pins request dmac activation. tend1 , tend0 output dma transfer end 1 and 0: these pins indicate the end of dmac data transfer. 16-bit timer- pulse unit (tpu) tclkd to tclka input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 i/o input capture/output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 i/o input capture/output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 i/o input capture/output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. serial communication interface (sci) txd2, txd1, txd0 output transmit data: data output pins. rxd2, rxd1, rxd0 input receive data: data input pins. sck2, sck1 sck0 i/o serial clock: clock i/o pins. d/a converter da0 output analog output: d/a converter analog output pins. avcc input this is the power supply pin for the d/a converter. when the d/a converter is not used, this pin should be connected to the system power supply (vcc). avss input this is the ground pin for the d/a converter. this pin should be connected to the system power supply (0 v). vref input this is the reference voltage input pin for the d/a converter. when the d/a converter is not used, this pin should be connected to the system power supply (vcc). 15 type symbol i/o name and function i/o ports p17 to p10 i/o port 1: an 8-bit i/o port. input or output can be designated for each bit by means of the port 1 data direction register (p1ddr). p36 to p30 i/o port 3: a 7-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p47 to p40 input port 4: an 8-bit input port. p77 to p70 i/o port 7: an 8-bit i/o port. input or output can be designated for each bit by means of the port 7 data direction register (p7ddr). p96 input port 9: a 1-bit input port. pa3 to pa0 i/o port a: a 4-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb7 to pb0 i/o port b: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc7 to pc0 i/o port c: an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). pd7 to pd0 i/o port d: an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr). pe7 to pe0 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr). pf7 to pf0 i/o port f: an 8-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). pg4 to pg0 i/o port g: a 5-bit i/o port. input or output can be designated for each bit by means of the port g data direction register (pgddr). 16 17 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2000 cpu has the following features. ? upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs ? general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) ? sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions ? eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @Cern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] ? 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally) 18 ? high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate : 16 mhz ? 8/16/32-bit register-register add/subtract : 62.5 ns ? 8 8-bit register-register multiply : 750 ns ? 16 8-bit register-register divide : 750 ns ? 16 16-bit register-register multiply : 1250 ns ? 32 16-bit register-register divide : 1250 ns ? two cpu operating modes ? normal mode* ? advanced mode note: * not available in the h8s/2214. ? power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. ? register configuration the mac register is supported only by the h8s/2600 cpu. ? basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. ? number of execution states the number of exection states of the mulxu and mulxs instructions. internal operation instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21 19 there are also differences in the address space, ccr and exr register functions, power-down state, etc., depending on the product. 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. ? more general registers and control registers ? eight 16-bit expanded registers, plus one 8-bit and two 32-bit control registers, have been added. ? expanded address space ? normal mode* supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. note: * not available in the h8s/2214. ? enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. ? higher speed ? basic instructions execute twice as fast. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. ? additional control register ? one 8-bit and two 32-bit control registers have been added. ? enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. 20 ? higher speed ? basic instructions execute twice as fast. 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal* and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally a maximum 16-mbyte program area and a maximum of 4 gbytes for program and data areas combined). the mode is selected by the mode pins of the microcontroller. note: * not available in the h8s/2214. cpu operating modes normal mode * note: * not available in the h8s/2214. advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbytes for program and data areas combined figure 2-1 cpu operating modes (1) normal mode (not available in the h8s/2214) the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@Crn) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid. 21 exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the configuration of the exception vector table in normal mode is shown in figure 2-2. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b power-on reset exception vector manual reset exception vector exception vector 1 exception vector 2 exception ' - (% 7 ' 4 2 # / 8 figure 2-2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table. 22 stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr * 3 pc (16 bits) sp sp notes: *1 *2 *3 when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 figure 2-3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used. 23 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved power-on reset exception vector (reserved for system use) reserved exception vector 1 reserved manual reset exception vector h'00000010 h'00000008 h'00000007 figure 2-4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table. 24 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1, * 3 ccr pc (24 bits) sp sp notes: *1 *2 *3 when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 reserved figure 2-5 stack structure in advanced mode 25 2.3 address space figure 2-6 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode * data area program area cannot be used by the h8s/2214 series note: * not available in the h8s/2214. figure 2-6 memory map 26 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2-7. there are two types of registers: general registers and control registers. t i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * in the h8s/2214, this bit cannot be used as an interrupt mask. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 half-carry flag user bit negative flag zero flag overflow flag carry flag h: u: n: z: v: c: figure 2-7 cpu registers 27 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2-8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2-8 usage of general registers 28 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2-9 shows the stack. free area stack area sp (er7) figure 2-9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). (1) program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr): this 8-bit register contains the trace bit (t) and interrupt mask bit. bit 7trace bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3reserved: these bits are reserved. they are always read as 1. 29 bits 2 to 0interrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr): this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7interrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. bit 6user bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. with the h8s/2214, this bit cannot be used as an interrupt mask bit. bit 5half-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4user bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3negative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2zero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1overflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0carry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: ? add instructions, to indicate a carry ? subtract instructions, to indicate a borrow ? shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions. 30 some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. 2.4.4 initial register values reset exception handling loads the cpus program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset. 31 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, , 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figures 2-10 and 2-11 show the data formats in general registers. 76543210 dont care 70 dont care 76543210 43 70 70 dont care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb dont care upper lower 43 70 dont care 70 dont care 70 general register er general register e general register r general register rh general register rl most significant bit least significant bit legend ern: en: rn: rnh: rnl: msb: lsb: figure 2-10 general register data formats (1) 32 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2-11 general register data formats (2) 33 2.5.2 memory data formats figure 2-12 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2-12 memory data formats when er7 is used as an address register to access the stack, the operand size should be word size or longword size. 34 2.6 instruction set 2.6.1 overview the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2-1. table 2-1 instruction classification function instructions size types data transfer mov bwl 5 pop* 1 , push* 1 wl ldm, stm l movfpe, movtpe* 3 b arithmetic add, sub, cmp, neg bwl 19 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas* 4 b logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc* 2 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total: 65 notes: b-byte size; w-word size; l-longword size. *1 pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. *2 bcc is the general name for conditional branch instructions. *3 cannot be used in the h8s/2214. *4 this instruction should be used with the er0, er1, er4, or er5 general register only. 35 2.6.2 instructions and addressing modes table 2-2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu can use. table 2-2 combinations of instructions and addressing modes addressing modes function data transfer arithmetic operations instruction mov bwl bwl bwl bwl bwl bwl b bwl bwl pop, push wl ldm, stm l add, cmp bwl bwl sub wl bwl addx, subx b b adds, subs l inc, dec bwl daa, das b neg bwl extu, exts wl tas * 2 b notes: *1 cannot be used in the h8s/2214. *2 this instruction should be used with the er0, er1, er4, or er5 general register only. movfpe * 1 , b movtpe * 1 mulxu, bw divxu mulxs, bw divxs #xx rn @ern @(d:16,ern) @(d:32,ern) @Cern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 36 addressing modes function logic operations system control block data transfer shift bit manipulation branch instruction and, or, bwl bwl xor andc, b orc, xorc bcc, bsr jmp, jsr rts trapa rte sleep ldc b b w w w w w w stc b w w w w w w not bwl bwl b b b b b nop bw legend b: byte w: word l: longword #xx rn @ern @(d:16,ern) @(d:32,ern) @Cern/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8 37 2.6.3 table of instructions classified by function table 2-3 summarizes the instructions in each functional category. the notation used in table 2-3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition C subtraction multiplication division logical and logical or logical exclusive or move ? not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 38 table 2-3 instructions classified by function type instruction size* 1 function data transfer mov b/w/l (eas) rd, rs (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in the h8s/2214. movtpe b cannot be used in the h8s/2214. pop w/l @sp+ rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn @Csp pushes a register onto the stack. push.w rn is identical to mov.w rn, @Csp. push.l ern is identical to mov.l ern, @Csp. ldm l @sp+ rn (register list) pops two or more general registers from the stack. stm l rn (register list) @Csp pushes two or more general registers onto the stack. note: *1 size refers to the operand size. b: byte w: word l: longword 39 type instruction size* 1 function arithmetic operations add sub b/w/l rd rs rd, rd #imm rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c rd, rd #imm c rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 rd, rd 2 rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 rd, rd 2 rd, rd 4 rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. mulxs b/w rd rs rd performs signed multiplication on data in two general registers: either 8 bits 8 bits 16 bits or 16 bits 16 bits 32 bits. divxu b/w rd rs rd performs unsigned division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder. note: *1 size refers to the operand size. b: byte w: word l: longword 40 type instruction size* 1 function arithmetic operations divxs b/w rd rs rd performs signed division on data in two general registers: either 16 bits 8 bits 8-bit quotient and 8-bit remainder or 32 bits 16 bits 16-bit quotient and 16- bit remainder. cmp b/w/l rd C rs, rd C #imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 C rd rd takes the twos complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd C 0, 1 ( 41 type instruction size* 1 function logic operations and b/w/l rd rs rd, rd #imm rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs rd, rd #imm rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd rs rd, rd #imm rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ? (rd) (rd) takes the ones complement of general register contents. shift operations shal shar b/w/l rd (shift) rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. note: *1 size refers to the operand size. b: byte w: word l: longword 42 type instruction size* 1 function bit- manipulation instructions bset b 1 ( 43 type instruction size* 1 function bit- manipulation instructions bxor bixor b b c ( 44 type instruction size function branch instructions bcc branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear c = 0 (high or same) bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n v = 0 blt less than n v = 1 bgt greater than z (n v) = 0 ble less or equal z (n v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine 45 type instruction size* 1 function system control trapa starts trap-instruction exception handling. instructions rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ccr, (eas) exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr (ead), exr (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ccr, exr #imm exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ccr, exr #imm exr logically ors the ccr or exr contents with immediate data. xorc b ccr #imm ccr, exr #imm exr logically exclusive-ors the ccr or exr contents with immediate data. nop pc + 2 pc only increments the program counter. note: *1 size refers to the operand size. b: byte w: word 46 type instruction size function block data transfer instruction eepmov.b eepmov.w if r4l 0 then repeat @er5+ @er6+ r4lC1 r4l until r4l = 0 else next; if r4 0 then repeat @er5+ @er6+ r4C1 r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed. 47 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc field). figure 2-13 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2-13 instruction formats (examples) (1) operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) condition field: specifies the branching condition of bcc instructions. 48 2.6.5 notes on use of bit-manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, carry out bit manipulation, then write back the byte of data. caution is therefore required when using these instructions on a register containing write-only bits, or a port. the bclr instruction can be used to clear internal i/o register flags to 0. in this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2-4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2-4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @Cern 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register directrn: the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers. 49 (2) register indirect@ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). (3) register indirect with displacement@(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. (4) register indirect with post-increment or pre-decrement@ern+ or @-ern: ? register indirect with post-increment@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. ? register indirect with pre-decrement@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. (5) absolute address@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2-5 indicates the accessible absolute address ranges. 50 table 2-5 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * not available in the h8s/2214. (6) immediate#xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative@(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is C126 to +128 bytes (C63 to +64 words) or C32766 to +32768 bytes (C16383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect@@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff* in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. note: * not available in the h8s/2214. 51 (a) normal mode * (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address note: * not available in the h8s/2214. figure 2-14 branch address specification in memory indirect mode if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) 2.7.2 effective address calculation table 2-6 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. 52 register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @Cern 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 dont care 24 23 dont care 24 23 dont care 24 23 dont care table 2-6 effective address calculation 53 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff dont care 24 23 dont care 24 23 dont care 24 23 dont care sign extension 54 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? normal mode * ? advanced mode note: * not available in the h8s/2214. 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents h'00 dont care 24 23 dont care dont care 55 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2-15 shows a diagram of the processing states. figure 2-16 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode and module stop mode. figure 2-15 processing states 56 end of bus request bus request program execution state bus-released state sleep mode exception-handling state external interrupt software standby mode mres = high res = high manual reset state * 1 power-on reset state * 1 reset state hardware standby mode * 2 notes: *1 *2 from any state except hardware standby mode, a transition to the power-on reset state occurs whenever res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs whenever mres goes low. a transition can also be made to the reset state when the watchdog timer overflows. from an y state, a transition to hardware standb y mode occurs when stby g oes low. sleep instruction with ssby = 0 sleep instruction with ssby = 1 interrupt request end of bus request bus request request for exception handling end of exception handling stby = high, res = low figure 2-16 state transitions 2.8.2 reset state when the res input goes low all current processing stops and the cpu enters the power-on reset state. when the mres input goes low, the cpu enters the manual reset state. all interrupts are disabled in the reset state. reset exception handling starts when the res or mres signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to section 11, watchdog timer. 57 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. (1) types of exception handling and their priority exception handling is performed for resets, traces, interrupts, and trap instructions. table 2-7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2-7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res or mres pin, or when the watchdog timer overflows. trace end of instruction execution or end of exception-handling sequence* 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence interrupt end of instruction execution or end of exception-handling sequence* 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed* 3 notes: *1 traces are enabled only in interrupt control mode 2. trace exception-handling is not executed at the end of the rte instruction. *2 interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. *3 trap instruction exception handling is always accepted, in the program execution state. 58 (2) reset exception handling after the res or mres pin has gone low and the reset state has been entered, reset exception handling starts when res or mres goes high again. the cpu enters the power-on reset state when the res pin is low, and the manual reset state when the mres pin is low. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. (3) traces traces are enabled only in interrupt control mode 2. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control mode 0, regardless of the state of the t bit. (4) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2-17 shows the stack after exception handling ends. 59 (c) interrupt control mode 0 (d) interrupt control mode 2 ccr pc (24 bits) sp notes: *1 ignored when returning. *2 not available in the h8s/2214. ccr pc (24 bits) sp exr reserved * 1 (a) interrupt control mode 0 (b) interrupt control mode 2 ccr ccr * 1 pc (16 bits) sp ccr ccr * 1 pc (16 bits) sp exr reserved * 1 normal mode * 2 advanced mode figure 2-17 stack structure after exception handling (examples) 60 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. there are two other bus masters in addition to the cpu: the dma controller (dmac) and data transfer controller (dtc). for further details, refer to section 6, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, software standby mode, and hardware standby mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. for details, refer to section 17, power- down state. (1) sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit in sbycr and the lson bit in lpwrcr are both cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. (2) software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1, and the lson bit in lpwrcr and the pss bit in tcsr (wdt1) are both cleared to 0. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. (3) hardware standby mode: a transition to hardware standby mode is made when the stby pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained. 61 2.9 basic timing 2.9.1 overview the cpu is driven by a system clock, denoted by the symbol ?. the period from one rising edge of ? to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2-18 shows the on-chip memory access cycle. figure 2-19 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus ? bus cycle t1 address read data write data read access write access figure 2-18 on-chip memory access cycle 62 bus cycle t1 unchanged address bus as rd hwr , lwr data bus ? high high high hi g h-im p edance state figure 2-19 pin states during on-chip memory access 63 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2-20 shows the access timing for the on-chip supporting modules. figure 2-21 shows the pin states. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus ? figure 2-20 on-chip supporting module access cycle 64 bus cycle t1 t2 unchanged address bus as rd hwr , lwr data bus ? high high high high-impedance state figure 2-21 pin states during on-chip supporting module access 2.9.4 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 6, bus controller. 2.10 usage note only register er0, er1, er4, or er5 should be used when using the tas instruction. the tas instruction is not generated by the hitachi h8s and h8/300 series c/c++ compilers. if the tas instruction is used as a user-defined intrinsic function, ensure that only register er0, er1, er4, or er5 is used. 65 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8s/2214 has four operating modes (modes 4 to 7). these modes enable selection of the cpu operating mode, enabling/disabling of on-chip rom, and the initial bus width setting, by setting the mode pins (md2 to md0). table 3-1 lists the mcu operating modes. table 3-1 mcu operating mode selection mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial width max. width 0 * 000 1 * 1 2 * 10 3 * 1 4 1 0 0 advanced on-chip rom disabled, expanded mode disabled 16 bits 16 bits 5 1 8 bits 16 bits 6 1 0 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode note: * not available in the h8s/2214. the cpus architecture allows for 4 gbytes of address space, but the h8s/2214 actually accesses a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. note that the functions of each pin depend on the operating mode. 66 the h8s/2214 can be used only in modes 4 to 7. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 3.1.2 register configuration the h8s/2214 has a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) that controls the operation of the h8s/2214. table 3-2 summarizes these registers. table 3-2 mcu registers name abbreviation r/winitial value address * mode control register mdcr r undetermined h'fde7 system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r note: * determined by pins md2 to md0. bit initial value r/w : : : mdcr is an 8-bit read-only register that indicates the current operating mode of the h8s/2214. bit 7reserved: read-only bit, always read as 1. bits 6 to 3reserved: read-only bits, always read as 0. bits 2 to 0mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read-only bits-they cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a power-on reset, but are retained after a manual reset. 67 3.2.2 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, the detected edge for nmi, and enables or disables mres pin input and on-chip ram. syscr is initialized to h'01 by a power-on reset and in hardware standby mode. in a manual reset, the intm1, intm0, nmieg, and rame bits are initialized, but the mrese bit is not. syscr is not initialized in software standby mode. bit 7reserved: only 0 should be written to this bit. bit 6reserved: read-only bit, always read as 0. bits 5 and 4interrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 control of interrupts by i bit (initial value) 1 setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 setting prohibited bit 3nmi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value) 1 an interrupt is requested at the rising edge of nmi input 68 bit 2manual reset select (mrese): enables or disables the mres pin. table 3-3 shows the relationship between the res and mres pin values and type of reset. for details of resets, see section 4.2, resets. bit 2 mrese description 0 manual reset is disabled p74/ mres pin can be used as p74 i/o pin (initial value) 1 manual reset is enabled p74/ mres pin can be used as mres input pin table 3-3 relationship between res and mres pin values and type of reset pins res mres type of reset 0 * power-on reset 1 0 manual reset 1 1 operating state * : dont care bit 1reserved: read-only bit, always read as 0. bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset status is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) note: when the dtc is used, the rame bit should not be cleared to 0. 69 3.3 operating mode descriptions 3.3.1 mode 4 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. pins p13 to p11 function as input ports immediately after a reset. address (a23 to a21) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pin 10 and ports a and b function as address (a20 to a8) outputs immediately after a reset. address output can be enabled or disabled by bits ae3 to ae0 in pfcr regardless of the corresponding ddr values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. port c always has an address (a7 to a0) output function. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 mode 5 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. pins p13 to p11 function as input ports immediately after a reset. address (a23 to a21) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pin 10 and ports a and b function as address (a20 to a8) outputs immediately after a reset. address output can be enabled or disabled by bits ae3 to ae0 in pfcr regardless of the corresponding ddr values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. port c always has an address (a7 to a0) output function. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 70 3.3.3 mode 6 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. pins p13 to p10, and ports a and b function as input ports immediately after a reset. address (a23 to a8) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. ports d and e function as a data bus, and part of port f carries data bus signals. port c is an input port immediately after a reset. addresses a7 to a0 are output by setting the corresponding ddr bits to 1. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.4 mode 7 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports. 71 3.4 pin functions in each operating mode the pin functions of ports 1, and a to f vary depending on the operating mode. table 3-3 shows their functions in each operating mode. table 3-3 pin functions in each mode port mode 4 mode 5 mode 6 mode 7 port 1 p13 to p11 p * /a p * /a p * /a p p10 p/a * p/a * p * /a p port a pa3 to pa0 p/a * p/a * p * /a p port b p/a * p/a * p * /a p port c a a p * /a p port d dddp port e p/d * p * /d p * /d p port f pf7 p/c * p/c * p/c * p * /c pf6 to pf4 cccp pf3 p/c * p * /c p * /c pf2 to pf0 p * /c p * /c p * /c legend p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset 3.5 memory map in each operating mode the h8s/2214 memory map is shown in figure 3-1. the address space is 16 mbytes in modes 4 to 7 (advanced modes). the address space is divided into eight areas for modes 4 to 7. for details, see section 6, bus controller. 72 external address space on-chip rom on-chip ram * note: internal i/o registers on-chip rom external address space external address space on-chip ram * reserved area * reserved area * on-chip ram on-chip ram * on-chip ram * on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'000000 h'020000 h'ffb000 h'ffc000 h'ffc000 h'ffefc0 h'ffffc0 h'ffb000 h'ffefc0 h'ffffc0 h'ffefbf h'ffc000 h'ffffc0 h'ffffff h'ffffff h'ffffff h'ffff40 h'ffff40 h'fff800 h'ffff3f h'ffff60 h'ffff60 h'ffff60 h'fff800 h'fff800 h'01ffff external addresses can be accessed by clearing the rame bit in syscr to 0. * modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-1 memory map in each operating mode in the h8s/2214 73 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4-1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. exception handling is prioritized as shown in table 4-1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times, in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits of syscr. table 4-1 exception handling types and priority priority exception handling type start of exception handling high reset starts immediately after a low-to-high transition at the res or mres pin, or when the watchdog timer overflows. the cpu enters the power-on reset state when the res pin is low, and the manual reset state when the mres pin is low. trace* 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 low trap instruction (trapa)* 3 started by execution of a trap instruction (trapa) notes: *1 traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. *2 interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. *3 trap instruction exception handling requests are accepted at all times in program execution state. 74 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extended register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception sources and vector table the exception sources are classified as shown in figure 4-1. different vector addresses are assigned to different exception sources. table 4-2 lists the exception sources and their vector addresses. exception sources reset trace direct transition interrupts trap instruction power-on reset manual reset external interrupts: nmi, irq7 to irq0 external expansion interrupts: exirq7 to exirq0 ( ! .# ! ! figure 4-1 exception sources 75 table 4-2 exception vector table vector address* 1 exception source vector number advanced mode power-on reset 0 h'0000 to h'0003 manual reset 1 h'0004 to h'0007 reserved for system use 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace 5 h'0014 to h'0017 direct transition 6 h'0018 to h'001b external interrupt nmi 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 irq2 18 h'0048 to h'004b irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 21 h'0054 to h'0057 irq6 22 h'0058 to h'005b irq7 23 h'005c to h'005f internal interrupt* 2 24 ? 111 h'0060 to h'0063 ? h'01bc to h'01bf notes: *1 lower 16 bits of the address. *2 for details of internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. 76 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the res or mres pin goes low, all processing halts and the h8s/2214 enters the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling begins when the res or mres pin changes from low to high. the levels of the res and mres pins at reset determine whether a power-on reset or a manual reset is effected. the h8s/2214 can also be reset by overflow of the watchdog timer. for details see section 11, watchdog timer. 4.2.2 reset types a reset can be of either of two types: a power-on reset or a manual reset. reset types are shown in table 4-3. a power-on reset should be used when powering on. the internal state of the cpu is initialized by either type of reset. a power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and i/o ports, which retain their previous states. with a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module i/o pins are switched to i/o ports controlled by ddr and dr. table 4-3 reset types reset transition conditions internal state type mres res cpu on-chip supporting modules power-on reset * low initialized initialized manual reset low high initialized initialized, except for bus controller and i/o ports * : dont care 77 a reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. when the mres pin is used, mres pin input must be enabled by setting the mrese bit to 1 in syscr. 4.2.3 reset sequence the h8s/2214 enters the reset state when the res or mres pin goes low. to ensure that the h8s/2214 is reset, hold the res or mres pin low for at least 20 ms at power- up. to reset the h8s/2214 during operation, hold the res or mres pin low for at least 20 states. when the res or mres pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4-2 and 4-3 show examples of the reset sequence. 78 internal address bus internal read signal internal write signal internal data bus (1) (3) vector fetch internal processing prefetch of first program instruction high (1) reset exception handling vector address (for a power-on reset, (1) = h'0000; for a manual reset, (1) = h'0002) (2) start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first program instruction (2) (4) ? res, mres figure 4-2 reset sequence (modes 2 and 3: not available in the h8s/2214) 79 address bus vector fetch internal processing prefetch of first program instruction (1) (3) reset exception handling vector address (for a power-on reset, (1) = h'000000, (3) = h'000002; for a manual reset, (1) = h'000004, (3) = h'000006) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction ? res, mres (1) (5) high (2) (4) (3) (6) rd hwr, lwr d15 to d0 * note: * three program wait states are inserted. ** figure 4-3 reset sequence (mode 4) 4.2.4 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx:32, sp). 4.2.5 state of on-chip supporting modules after reset release after reset release, mstpcra is initialized to h'3f, mstpcrb and mstpcrc are initialized to h'ff, and all modules except the dmac and dtc enter module stop mode. consequently, on- chip supporting module registers cannot be read or written to. register reading and writing is enabled when module stop mode is exited. 80 4.3 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is canceled by clearing the t bit in exr to 0. it is not affected by interrupt masking. table 4-4 shows the state of ccr and exr after execution of trace exception handling. interrupts are accepted even within the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4-4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 210 legend 1: set to 1 0: cleared to 0 : retains value prior to execution. 81 4.4 interrupts interrupt exception handling can be requested by nine external sources (nmi, irq7 to irq0), eight external expansion sources (exirq7 to exirq0), and 31 internal sources in the on-chip supporting modules. figure 4-4 classifies the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit timer-pulse unit (tpu), serial communication interface (sci), data transfer controller (dtc), and dma controller (dmac). each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details of interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq7 to irq0 (8) wdt * (1) tpu (13) sci (12) dtc (1) dmac (4) numbers in parentheses are the numbers of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. notes: external expansion interrupts: exirq7 to exirq0 (8) figure 4-4 interrupt sources and number of interrupts 82 4.5 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4-5 shows the status of ccr and exr after execution of trap instruction exception handling. table 4-5 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 01 210 legend 1: set to 1 0: cleared to 0 : retains value prior to execution. 83 4.6 stack status after exception handling figures 4-5 and 4-6 show the stack after completion of trap instruction exception handling and interrupt exception handling. sp sp ccr ccr * pc (16 bits) ccr ccr * pc (16 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 stack status after exception handling (normal modes: not available in the h8s/2214) sp sp ccr pc (24bits) ccr pc (24bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-6 stack status after exception handling (advanced modes) 84 4.7 notes on use of the stack when accessing word data or longword data, the h8s/2214 assumes that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4-7 shows an example of what happens when the sp value is odd. sp legend note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @Cer7 sp set to h'fffeff trap instruction executed data saved above sp contents of ccr lost ccr: condition code register pc: program counter r1l: general register r1l sp: stack pointer figure 4-7 operation when sp value is odd 85 section 5 interrupt controller 5.1 overview 5.1.1 features the h8s/2214 controls interrupts by means of an interrupt controller. the interrupt controller has the following features: ? two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). ? priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. ? independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. ? nine external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq7 to irq0. ? dtc or dmac control ? dtc or dmac activation is performed by means of interrupts. ? eight external expansion interrupt input pins 86 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5-1. syscr nmi input irq input internal interrupt request swdtend to tei2 intm1 intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i, ui i2 to i0 ccr exr cpu iscr ier isr ipr syscr : irq sense control register : irq enable register : irq status register : interrupt priority register : system control register legend external expansion interrupt sources exirq0 to exirq7 figure 5-1 block diagram of interrupt controller 87 5.1.3 pin configuration table 5-1 summarizes the pins of the interrupt controller. table 5-1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected external expansion interrupt sources 7 to 0 exirq7 to exirq0 input interrupts from external expansion modules. interrupt is accepted on low level. 5.1.4 register configuration table 5-2 summarizes the registers of the interrupt controller. table 5-2 interrupt controller registers name abbreviation r/w initial value address* 1 system control register syscr r/w h'01 h'fde5 irq sense control register h iscrh r/w h'00 h'fe12 irq sense control register l iscrl r/w h'00 h'fe13 irq enable register ier r/w h'00 h'fe14 irq status register isr r/(w)* 2 h'00 h'fe15 interrupt priority register a ipra r/w h'77 h'fec0 interrupt priority register b iprb r/w h'77 h'fec1 interrupt priority register c iprc r/w h'77 h'fec2 interrupt priority register d iprd r/w h'77 h'fec3 interrupt priority register f iprf r/w h'77 h'fec5 interrupt priority register giprg r/w h'77 h'fec6 interrupt priority register j iprj r/w h'77 h'fec9 interrupt priority register k iprk r/w h'77 h'feca interrupt priority register m iprm r/w h'77 h'fecc notes: *1 lower 16 bits of the address. *2 can only be written with 0 for flag clearing. 88 5.2 register descriptions 5.2.1 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'01 by a power-on reset and in hardware standby mode. in a manual reset, the intm1, intm0, nmieg, and rame bits are initialized, but the mrese bit is not. syscr is not initialized in software standby mode. bits 5 and 4interrupt control mode 1 and 0 (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 setting prohibited bit 3nmi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input 89 5.2.2 interrupt priority registers a to d, f, g, j, k, m (ipra to iprd, iprf, iprg, iprj, iprk, iprm) 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w : : : the ipr registers are nine 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between ipr settings and interrupt sources is shown in table 5-3. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'77 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 7 and 3reserved: read-only bits, always read as 0. table 5-3 correspondence between interrupt sources and ipr settings bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2 irq3 irq4 irq5 iprc irq6 irq7 dtc iprd watchdog timer 0 * iprf tpu channel 0 tpu channel 1 iprgtpu channel 2 iprj dmac sci channel 0 iprk sci channel 1 sci channel 2 iprm exirq3 to exirq0 exirq7 to exirq4 note: * reserved bits. these bits cannot be modified and are always read as 1. 90 as shown in table 5-3, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 5.2.3 irq enable register (ier) 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq7 to irq0. ier is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0irq7 to irq0 enable (irq7e to irq0e): these bits select whether irq7 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value) 1 irqn interrupts enabled (n = 7 to 0) 91 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : iscrl 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : the iscr registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq7 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 15 to 0: irq7 sense control a and b (irq7sca, irq7scb) to irq0 sense control a and b (irq0sca, irq0scb) bits 15 to 0 irq7scb to irq0scb irq7sca to irq0sca description 0 0 interrupt request generated at irq7 to irq0 input low level (initial value) 1 interrupt request generated at falling edge of irq7 to irq0 input 1 0 interrupt request generated at rising edge of irq7 to irq0 input 1 interrupt request generated at both falling and rising edges of irq7 to irq0 input 92 5.2.5 irq status register (isr) 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * only 0 can be written, to clear the flag. : : : isr is an 8-bit readable/writable register that indicates the status of irq7 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bits 7 to 0irq7 to irq0 flags (irq7f to irq0f): these bits indicate the status of irq7 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 7 to 0) 93 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq7 to irq0) and internal interrupts (53 sources). 5.3.1 external interrupts there are nine external interrupts: nmi and irq7 to irq0. of these, nmi and irq2 to irq0 can be used to restore the h8s/2214 from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq7 to irq0 interrupts: interrupts irq7 to irq0 are requested by an input signal at pins irq7 to irq0 . interrupts irq7 to irq0 have the following features: ? using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0 . ? enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. ? the interrupt priority level can be set with ipr. ? the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq7 to irq0 is shown in figure 5-2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n = 7 to 0 figure 5-2 block diagram of interrupts irq7 to irq0 94 figure 5-3 shows the timing of setting irqnf. ? irqn input pin irqnf figure 5-3 timing of setting irqnf the vector numbers for irq7 to irq0 interrupt exception handling are 23 to 16. detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 and use the pin as an i/o pin for another function. since interrupt request flags irq7f to irq0f are set when the setting condition is satisfied, regardless of the ier setting, only the necessary flags should be referenced. exirq7 to exirq0 interrupts: interrupts exirq7 to exirq0 are for use by external expansion modules. an interrupt is requested by a low-level input signal at one of pins exirq7 to exirq0. 5.3.2 internal interrupts there are 31 sources for internal interrupts from on-chip supporting modules. ? for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. ? the interrupt priority level can be set by means of ipr. ? the dmac and dtc can be activated by a tpu, 8-bit timer, sci, or other interrupt request. when the dmac and dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 interrupt exception handling vector table table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. 95 priorities among modules can be set by means of the ipr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5- 4. table 5-4 interrupt sources, vector addresses, and interrupt priorities origin of vector address * interrupt source interrupt source vector number advanced mode ipr priority nmi external 7 h'001c high irq0 pin 16 h'0040 ipra6 to ipra 4 irq1 17 h'0044 ipra2 to ipra 0 irq2 irq3 18 19 h'0048 h'004c iprb6 to iprb 4 irq4 irq5 20 21 h'0050 h'0054 iprb2 to iprb 0 irq6 irq7 22 23 h'0058 h'005c iprc6 to iprc 4 swdtend (software activation interrupt end) dtc 24 h'0060 iprc2 to iprc 0 wovi0 (interval timer) watchdog timer 0 25 h'0064 iprd6 to iprd 4 tgi0a (tgr0a input capture/compare match) tgi0b (tgr0b input capture/compare match) tgi0c (tgr0c input capture/compare match) tgi0d (tgr0d input capture/compare match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0080 h'0084 h'0088 h'008c h'0090 iprf6 to iprf 4 reserved 37 38 39 h'0094 h'0098 h'009c low note: * lower 16 bits of the start address. 96 origin of vector address * interrupt source interrupt source vector number advanced mode ipr priority tgi1a (tgr1a input capture/compare match) tgi1b (tgr1b input capture/compare match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'00a0 h'00a4 h'00a8 h'00ac iprf2 to iprf 0 high tgi2a (tgr2a input capture/compare match) tgi2b (tgr2b input capture/compare match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'00b0 h'00b4 h'00b8 h'00bc iprg6 to iprg 4 dend0a (channel 0/channel 0a transfer end) dend0b (channel 0b transfer end) dend1a (channel 1/channel 1a transfer end) dend1b (channel 1b transfer end) dmac 72 73 74 75 h'0120 h'0124 h'0128 h'012c iprj6 to iprj4 eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'0140 h'0144 h'0148 h'014c iprj2 to iprj 0 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'0150 h'0154 h'0158 h'015c iprk6 to iprk 4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 88 89 90 91 h'0160 h'0164 h'0168 h'016c iprk2 to iprk 0 exirq0 exirq1 exirq2 exirq3 external module 104 105 106 107 h'01a0 h'01a4 h'01a8 h'01ac iprm6 to iprm4 exirq4 exirq5 exirq6 exirq7 108 109 110 111 h'01b0 h'01b4 h'01b8 h'01dc iprm2 to iprm0 low note: * lower 16 bits of the start address. 97 5.4 interrupt operation 5.4.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2214 differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5-5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr, and the masking state indicated by the i and ui bits in the cpus ccr, and bits i2 to i0 in exr. table 5-5 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 registers mask bits description 0 0 0 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited 98 figure 5-4 shows a block diagram of the priority decision circuit. interrupt acceptance control 8-level mask control default priority determination vector number interru p t control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5-4 block diagram of interrupt control operation (1) interrupt acceptance control in interrupt control mode 0, interrupt acceptance is controlled by the i bit in ccr. table 5-6 shows the interrupts selected in each interrupt control mode. table 5-6 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts * : don't care 99 (2) 8-level control in interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5-7 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0). (3) default priority determination when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5-8 shows operations and control signal functions in each interrupt control mode. table 5-8 operations and control signal functions in each interrupt control mode interrupt control setting interrupt acceptance control 8-level control default priority t mode intm1 intm0 i i2 to i0 ipr determination (trace) 000 im x * 2 210 x * 1 im pr t legend : interrupt operation control performed x : no operation. (all interrupts enabled) im : used as interrupt mask bit pr : sets priority. : not used. notes: *1 set to 1 when interrupt is accepted. *2 keep the initial setting. 100 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpus ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. [3] interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] next, the i bit in ccr is set to 1. this masks all interrupts except nmi. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 101 program execution status interrupt generated? nmi irq0 irq1 tei3 i=0 save pc and ccr i 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5-5 flowchart of procedure up to interrupt acceptance in interrupt control mode 0 102 5.4.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 103 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5-6 flowchart of procedure up to interrupt acceptance in interrupt control mode 2 104 5.4.4 interrupt exception handling sequence figure 5-7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data us ? (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5-7 interrupt exception handling 105 5.4.5 interrupt response times the h8s/2214 is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5-9 are explained in table 5-10. table 5-9 interrupt response times normal mode* 5 advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination* 1 33 33 2 number of wait states until executing instruction ends* 2 (1 to 19) + 2s i (1 to 19) + 2s i (1 to 19) + 2s i (1 to 19) + 2s i 3 pc, ccr, exr stack save 2s k 3s k 2s k 3s k 4 vector fetch s i s i 2s i 2s i 5 instruction fetch* 3 2s i 2s i 2s i 2s i 6 internal processing* 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: *1 two states in case of internal interrupt. *2 refers to mulxs and divxs instructions. *3 prefetch after interrupt acceptance and interrupt handling routine prefetch. *4 internal processing after interrupt acceptance and internal processing after vector fetch. *5 not available in the h8s/2214. table 5-10 number of states in interrupt handling routine execution statuses object of access external device 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6 + 2 m 2 3 + m branch address read s j stack manipulation s k m: number of wait states in an external device access. 106 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5-8 shows and example in which the tgiea bit in 16-bit timer tier0 is cleared to 0. internal address bus internal write signal ? tgiea tgfa tgioa interrupt signal tier0 write cycle by cpu tgioa exception handling tier0 address figure 5-8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 107 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 times when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. 5.5.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction. with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 108 5.6 dtc and dmac activation by interrupt 5.6.1 overview the dtc and dmac can be activated by an interrupt. in this case, the following options are available: ? interrupt request to cpu ? activation request to dtc ? activation request to dmac ? selection of a number of the above for details of interrupt requests that can be used with to activate the dtc and dmac, see section 8, data transfer controller and section 7, dma controller. 5.6.2 block diagram figure 5-9 shows a block diagram of the dtc interrupt controller. dmac selection circuit dtcer dtvecr control logic determination of priority cpu dtc select signal irq interrupt on-chip supporting module disenable signal clear signal clear signal interrupt controller i, i2 to i0 interrupt source clear signal interrupt request dtc activation request vector number cpu interrupt request vector number swdte clear signal clear signal figure 5-9 interrupt control for dtc and dmac 109 5.6.3 operation the interrupt controller has three main functions in dtc and dmac control. (1) selection of interrupt source: dmac inputs activation factor directly to each channel. the activation factors for each channel of dmac are selected by dtf3 to dtf0 bits of dmacr. the dta bit of dmabcr can be used to select whether the selected activation factors are managed by dmac. by setting the dta bit to 1, the interrupt factor which were the activation factor for that dmac do not act as the dtc activation factor or the cpu interrupt factor. interrupt factors other than the interrupts managed by the dmac are selected as dtc activation request or cpu interrupt request by the dtcea to dtcef of dtc and the dtce bit of dtcei. by specifying the disel bit of the dtc's mrb, it is possible to clear the dtce bit to 0 after dtc data transfer, and request a cpu interrupt. if dtc carries out the designate number of data transfers and the transfer counter reads 0, after dtc data transfer, the dtce bit is also cleared to 0, and a cpu interrupt requested. (2) determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see 8.4 interrupts and 8.3.3 dtc vector table for the respective priority. (3) operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. if the same interrupt is selected as the dmac activation factor and as the dtc activation factor or cpu interrupt factor, these operate independently. they operate in accordance with the respective operating states and bus priorities. table 5-11 shows the interrupt factor clear control and selection of interrupt factors by specification of the dta bit of dmac's dmabcr, dtc's dtcea to dtcef, dtcei's dtce bits, and the disel bit of dtc's mrb. 110 table 5-11 interrupt source selection and clearing control settings dmac dtc interrupt sources selection/clearing control dta dtce disel dmac dtc cpu 00 * x 10 x 1 1 ** xx legend : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. x : the relevant bit cannot be used. * : dont care (4) notes on use: the sci interrupt source is cleared when the dmac or dtc reads or writes to the prescribed register, and is not dependent upon the dta bit, dtce bit, or disel bit. 111 section 6 bus controller 6.1 overview the h8s/2214 has a built-in bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu, dma controller (dmac), and data transfer controller (dtc). 6.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as 8 areas of 2-mbytes ? bus specifications can be set independently for each area ? burst rom interface can be set ? basic bus interface ? chip select ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu, dmac, and dtc ? other features ? external bus release function 112 6.1.2 block diagram figure 6-1 shows a block diagram of the bus controller. area decoder bus controller abwcr astcr bcrh bcrl internal address bus cs0 to cs7 external bus control signals breq back internal control signals wait controller wcrh wcrl bus mode signal bus arbiter cpu bus request signal dtc bus request signal dmac bus request signal cpu bus acknowledge signal dtc bus acknowledge signal dmac bus acknowledge signal wait internal data bus figure 6-1 block diagram of bus controller 113 6.1.3 pin configuration table 6-1 summarizes the pins of the bus controller. table 6-1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write hwr output strobe signal indicating that external space is to be written, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d7 to d0) of data bus is enabled. chip select 0 to 7 cs0 to cs7 output strobe signal indicating that areas 0 to 7 are selected. wait wait input wait request signal when accessing external 3-state access space. bus request breq input request signal that releases bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released. 114 6.1.4 register configuration table 6-2 summarizes the registers of the bus controller. table 6-2 bus controller registers initial value name abbreviation r/w power-on reset manual reset address* 1 bus width control register abwcr r/w h'ff/h'00* 2 retained h'fed0 access state control register astcr r/w h'ff retained h'fed1 wait control register h wcrh r/w h'ff retained h'fed2 wait control register l wcrl r/w h'ff retained h'fed3 bus control register h bcrh r/w h'd0 retained h'fed4 bus control register l bcrl r/w h'08 retained h'fed5 pin function control register pfcr r/w h'0d/h'00* 3 retained h'fdeb notes: *1 lower 16 bits of the address. *2 determined by the mcu operating mode. initialized to h'00 in mode 4, and to h'ff in modes 5 to 7. *3 initialized to h'0d in modes 4 and 5, and to h'00 in modes 6 and 7. 115 6.2 register descriptions 6.2.1 bus width control register (abwcr) 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : rw initial value : : rw abwcr is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. after a power-on reset and in hardware standby mode, abwcr is initialized to h'ff in modes 5, 6, and 7, and to h'00 in mode 4. it is not initialized by a manual reset or in software standby mode. bits 7 to 0area 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0) 116 6.2.2 access state control register (astcr) 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : astcr is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. astcr is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bits 7 to 0area 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space is disabled 1 area n is designated for 3-state access (initial value) wait state insertion in area n external space is enabled (n = 7 to 0) 117 6.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in the case of on-chip memory or internal i/o registers. wcrh and wcrl are initialized to h'ff by a power-on reset and in hardware standby mode. they are not initialized by a manual reset or in software standby mode. (1) wcrh 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : bits 7 and 6area 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 bit 6 w71 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value) 118 bits 5 and 4area 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 bit 4 w61 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) bits 3 and 2area 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 bit 2 w51 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0area 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 bit 0 w41 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value) 119 (2) wcrl 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : bits 7 and 6area 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 bit 6 w31 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4area 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 bit 4 w21 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value) 120 bits 3 and 2area 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 bit 2 w11 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0area 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 bit 0 w01 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value) 121 6.2.4 bus control register h (bcrh) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. bcrh is initialized to h'd0 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7idle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas 1 idle cycle inserted in case of successive external read cycles in different areas (initial value) bit 6idle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value) bit 5burst rom enable (brstrm): selects whether area 0 is used as a burst rom interface. bit 5 brstrm description 0 area 0 is basic bus interface (initial value) 1 area 0 is burst rom interface 122 bit 4burst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value) bit 3burst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value) 1 max. 8 words in burst access bits 2 to 0reserved: only 0 should be written to these bits. 123 6.2.5 bus control register l (bcrl) 7 brle 0 r/w 6 0 r/w 5 0 4 0 r/w 3 1 r/w 0 waite 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of wait pin input. bcrl is initialized to h'08 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7bus release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release is disabled. breq and back can be used as i/o ports. (initial value) 1 external bus release is enabled. bit 6reserved: only 0 should be written to this bit. bit 5reserved: this bit cannot be modified and is always read as 0. bit 4reserved: only 0 should be written to this bit. bit 3reserved: only 1 should be written to this bit. bits 2 and 1reserved: only 0 should be written to these bits. bit 0wait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port. (initial value) 1 wait input by wait pin enabled 124 6.2.6 pin function control register (pfcr) 7 0 0 r/w 6 0 0 r/w 5 0 0 r/w 4 0 0 r/w 3 ae3 1 0 r/w 0 ae0 1 0 r/w 2 ae2 1 0 r/w 1 ae1 0 0 r/w bit : modes 4 and 5 initial value : modes 6 and 7 initial value : r/w : pfcr is an 8-bit readable/writable register that performs address output control in external expanded mode. pfcr is initialized to h'0d (modes 4 and 5) or h'00 (modes 6 and 7) by a power-on reset and in hardware standby mode. it retains its previous state in a manual reset and in software standby mode. bits 7 to 4reserved: only 0 should be written to these bits. bits 3 to 0address output enable 3 to 0 (ae3 to ae0): these bits select enabling or disabling of address outputs a8 to a23 in romless expanded mode and modes with rom. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1. 125 bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0000 a8 to a23 output disabled (initial value* 1 ) 1 a8 output enabled; a9 to a23 output disabled 1 0 a8, a9 output enabled; a10 to a23 output disabled 1 a8 to a10 output enabled; a11 to a23 output disabled 1 0 0 a8 to a11 output enabled; a12 to a23 output disabled 1 a8 to a12 output enabled; a13 to a23 output disabled 1 0 a8 to a13 output enabled; a14 to a23 output disabled 1 a8 to a14 output enabled; a15 to a23 output disabled 1000 a8 to a15 output enabled; a16 to a23 output disabled 1 a8 to a16 output enabled; a17 to a23 output disabled 1 0 a8 to a17 output enabled; a18 to a23 output disabled 1 a8 to a18 output enabled; a19 to a23 output disabled 1 0 0 a8 to a19 output enabled; a20 to a23 output disabled 1 a8 to a20 output enabled; a21 to a23 output disabled (initial value* 2 ) 1 0 a8 to a21 output enabled; a22, a23 output disabled 1 a8 to a23 output enabled notes: *1 in expanded mode with rom, bits ae3 to ae0 are initialized to b'0000. in expanded mode with rom, address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1. *2 in romless expanded mode, bits ae3 to ae0 are initialized to b'1101. in romless expanded mode, address pins a0 to a7 are always made address output. 126 6.3 overview of bus control 6.3.1 area divisions in advanced mode, the bus controller partitions the 16 mbytes address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. in normal mode*, it controls a 64-kbyte address space comprising part of area 0 (not available in the h8s/2214). figure 6-2 shows an outline of the memory map. chip select signals ( cs0 to cs7 ) can be output for each area. note: * not available in the h8s/2214. area 0 (2mbytes) h'000000 h'ffffff (1) (2) h'0000 h'1fffff h'200000 area 1 (2mbytes) h'3fffff h'400000 area 2 (2mbytes) h'5fffff h'600000 area 3 (2mbytes) h'7fffff h'800000 area 4 (2mbytes) h'9fffff h'a00000 area 5 (2mbytes) h'bfffff h'c00000 area 6 (2mbytes) h'dfffff h'e00000 area 7 (2mbytes) h'ffff advanced mode normal mode * note: * not available in the h8s/2214. figure 6-2 overview of area divisions 127 6.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. (1) bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. when the burst rom interface is designated, 16-bit bus mode is always set. (2) number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3- state access is selected functions as a 3-state access space. with the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. (3) number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 6-3 shows the bus specifications for each basic bus interface area. 128 table 6-3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0016 2 0 100 3 0 11 10 2 13 108 2 0 100 3 0 11 10 2 13 6.3.3 memory interfaces the h8s/2214 memory interfaces comprise a basic bus interface that allows direct connection of rom, sram, and so on, and a burst rom interface (for area 0 only) that allows direct connection of burst rom. an area for which the basic bus interface is designated functions as normal space, and an area for which the burst rom interface is designated functions as burst rom space. 129 6.3.4 interface specifications for each area the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (6.4 and 6.5) should be referred to for further details. area 0: area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. when area 0 external space is accessed, the cs0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. areas 1 to 6: in external expansion mode, all of areas 1 to 6 is external space. when area 1 to 6 external space is accessed, the cs1 to cs6 pin signals respectively can be output. only the basic bus interface can be used for areas 1 to 6. area 7: area 7 includes the on-chip ram, external module expansion function space, and internal l/o registers. in external expansion mode, the space excluding the on-chip ram, external module expansion function space, and internal l/o registers, is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. when the p75msoe bit in the external module connection output pin select register (opinsel) is set to 1, the external module expansion function is enabled and the signal is output for addresses h'ffff40 to h'ffff5f. when the p75msoe bit is cleared to 0, the external module expansion function is disabled and the corresponding addresses are external space. when area 7 external space is accessed, the cs7 signal can be output. only the basic bus interface can be used for the area 7. 130 6.3.5 chip select signals the h8s/2214 can output chip select signals ( cs0 to cs7 ) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. figure 6-3 shows an example of csn (n = 0 to 7) output timing. enabling or disabling of the csn signal is performed by setting the data direction register (ddr) for the port corresponding to the particular csn pin. in rom-disabled expansion mode, the cs0 pin is placed in the output state after a power-on reset. pins cs1 to cs7 are placed in the input state after a power-on reset, and so the corresponding ddr should be set to 1 when outputting signals cs1 to cs7 . in rom-enabled expansion mode, pins cs0 to cs7 are all placed in the input state after a power- on reset, and so the corresponding ddr should be set to 1 when outputting signals cs0 to cs7 . for details, see section 9, i/o ports. bus cycle t 1 t 2 t 3 area n external address address bus ? csn figure 6-3 csn signal output timing (n = 0 to 7) 131 6.4 basic bus interface 6.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 6- 3). 6.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 6-4 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 6-4 access sizes and data alignment control (8-bit access space) 132 16-bit access space: figure 6-5 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7 d0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size ? even address byte size ? odd address lower data bus figure 6-5 access sizes and data alignment control (16-bit access space) 133 6.4.3 valid strobes table 6-4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid without discrimination between the upper and lower halves of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 6-4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) 8-bit access byte read rd valid invalid space write hwr hi-z 16-bit access byte read even rd valid invalid space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read rd valid valid write hwr , lwr valid valid note: hi-z: high impedance. invalid: input state; input value is ignored. 134 6.4.4 basic timing 8-bit 2-state access space: figure 6-6 shows the bus timing for an 8-bit 2-state access space. when an 8-bit access space is accessed , the upper half (d15 to d8) of the data bus is used. wait states cannot be inserted. bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr (16-bit bus mode) d15 to d8 valid d7 to d0 write note: n = 0 to 7 high high impedance lwr (8-bit bus mode) high impedance figure 6-6 bus timing for 8-bit 2-state access space 135 8-bit 3-state access space: figure 6-7 shows the bus timing for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states can be inserted. bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 invalid read hwr d15 to d8 valid d7 to d0 high impedance write note: n = 0 to 7 t3 lwr (16-bit bus mode) lwr (8-bit bus mode) high high impedance figure 6-7 bus timing for 8-bit 3-state access space 136 16-bit 2-state access space: figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states cannot be inserted. bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 write high note: n = 0 to 7 high impedance figure 6-8 bus timing for 16-bit 2-state access space (1) (even address byte access) 137 bus cycle t1 t2 address bus ? csn as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 d7 to d0 valid write note: n = 0 to 7 high high impedance figure 6-9 bus timing for 16-bit 2-state access space (2) (odd address byte access) 138 bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 figure 6-10 bus timing for 16-bit 2-state access space (3) (word access) 139 16-bit 3-state access space: figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. when a 16-bit access space is accessed , the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states can be inserted. bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high note: n = 0 to 7 t3 figure 6-11 bus timing for 16-bit 3-state access space (1) (even address byte access) 140 bus cycle t1 t2 address bus ? csn as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 d7 to d0 valid write high note: n = 0 to 7 t3 high impedance figure 6-12 bus timing for 16-bit 3-state access space (2) (odd address byte access) 141 bus cycle t1 t2 address bus ? csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 t3 figure 6-13 bus timing for 16-bit 3-state access space (3) (word access) 142 6.4.5 wait control when accessing external space, the h8s/2214 can extend the bus cycle by inserting one or more wait states (tw). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. program wait insertion from 0 to 3 wait states can be inserted automatically between the t2 state and t3 state on an individual area basis in 3-state access space, according to the settings of wcrh and wcrl. pin wait insertion setting the waite bit in bcrh to 1 enables wait insertion by means of the wait pin. when external space is accessed in this state, program wait insertion is first carried out according to the settings in wcrh and wcrl. then , if the wait pin is low at the falling edge of ? in the last t2 or tw state, a tw state is inserted. if the wait pin is held low, tw states are inserted until it goes high. this is useful when inserting four or more tw states, or when changing the number of tw states for different external devices. the waite bit setting applies to all areas. 143 figure 6-14 shows an example of wait state insertion timing. by program wait t1 address bus ? as rd data bus read data read hwr, lwr write data write note: indicates the timing of wait pin sampling. wait data bus t2 tw tw tw t3 by wait pin figure 6-14 example of wait state insertion timing the settings after a power-on reset are: 3-state access, 3 program wait state insertion, and wait input disabled. when a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. 144 6.5 burst rom interface 6.5.1 overview with the h8s/2214, external space area 0 can be designated as burst rom space, and burst rom interfacing can be performed. the burst rom space interface enables 16-bit configuration rom with burst access capability to be accessed at high speed. area 0 can be designated as burst rom space by means of the brstrm bit in bcrh. consecutive burst accesses of a maximum of 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. 6.5.2 basic timing the number of states in the initial cycle (full access) of the burst rom interface is in accordance with the setting of the ast0 bit in astcr. also, when the ast0 bit is set to 1, wait state insertion is possible. one or two states can be selected for the burst cycle, according to the setting of the brsts1 bit in bcrh. wait states cannot be inserted. when area 0 is designated as burst rom space, it becomes 16-bit access space regardless of the setting of the abw0 bit in abwcr. when the brsts0 bit in bcrh is cleared to 0, burst access of up to 4 words is performed; when the brsts0 bit is set to 1, burst access of up to 8 words is performed. the basic access timing for burst rom space is shown in figures 6-15 and 6-16. the timing shown in figure 6-15 is for the case where the ast0 and brsts1 bits are both set to 1, and that in figure 6-16 is for the case where both these bits are cleared to 0. 145 t1 address bus ? cs0 as data bus t2 t3 t1 t2 t1 full access t2 rd burst access only lower address changed read data read data read data figure 6-15 example of burst rom access timing (when ast0 = brsts1 = 1) 146 t1 address bus ? cs0 as data bus t2 t1 t1 full access rd burst access only lower address changed read data read data read data figure 6-16 example of burst rom access timing (when ast0 = brsts1 = 0) 6.5.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) of the burst rom interface. see section 6.4.5, wait control. wait states cannot be inserted in a burst cycle. 147 6.6 idle cycle 6.6.1 operation when the h8s/2214 accesses external space , it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on. (1) consecutive reads between different areas if consecutive reads between different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. figure 6-17 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t1 address bus ? rd bus cycle a " & = = = ( floating time data collision (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) t1 address bus ? rd data bus t2 t3 ti t1 t2 cs (area a) cs (area b) cs (area a) cs (area b) figure 6-17 example of idle cycle operation (1) 148 (2) write after read if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 6-18 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t1 address bus ? rd bus cycle a data bus t2 t3 t1 t2 bus cycle b long output floating time data collision t1 address bus ? rd bus cycle a data bus t2 t3 ti t1 bus cycle b t2 hwr hwr cs (area a) cs (area b) cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 6-18 example of idle cycle operation (2) 149 (3) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the systems load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 6-19. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. t1 address bus ? rd bus cycle a t2 t3 t1 t2 bus cycle b possibility of overlap between cs (area b) and rd t1 address bus ? bus cycle a t2 t3 ti t1 bus cycle b t2 cs (area a) cs (area b) rd cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 6-19 relationship between chip select ( cs ) and read ( rd ) 150 6.6.2 pin states in idle cycle table 6-5 shows pin states in an idle cycle. table 6-5 pin states in idle cycle pins pin state a23 to a0 contents of next bus cycle d15 to d0 high impedance csn high as high rd high hwr high lwr high dackn high 151 6.7 bus release 6.7.1 overview the h8s/2214 can release the external bus in response to a bus request from an external device. in the external bus released state, the internal bus master continues to operate as long as there is no external access. 6.7.2 operation in external expansion mode, the bus can be released to an external device by setting the brle bit in bcrl to 1. driving the breq pin low issues an external bus request to the h8s/2214. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. in the external bus released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. in the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low) 152 6.7.3 pin states in external bus released state table 6-6 shows pin states in the external bus released state. table 6-6 pin states in bus released state pins pin state a23 to a0 high impedance d15 to d0 high impedance csn high impedance as high impedance rd high impedance hwr high impedance lwr high impedance dackn high level 153 6.7.4 transition timing figure 6-20 shows the timing for transition to the bus-released state. cpu cycle external bus released state cpu cycle address minimum 1 state t0 t1 t2 ? address bus data bus csn as hwr , lwr breq back high impedance [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] note: n = 0 to 7 low level of breq pin is sampled at rise of t2 state. back pin is driven low at end of cpu read cycle, releasing bus to external bus master. breq pin state is still sampled in external bus released state. high level of breq pin is sampled. back pin is driven high, ending bus release cycle. high impedance high impedance high impedance high impedance rd high impedance figure 6-20 bus-released state transition timing 154 6.7.5 usage note when mstpcr is set to h'ffffff and a transition is made to sleep mode, the external bus release function halts. therefore, mstpcr should not be set to h'ffffff if the external bus release function is to be used in sleep mode. 6.8 bus arbitration 6.8.1 overview the h8s/2214 has a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu, dmac, and dtc, which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 6.8.2 operation the bus arbiter detects the bus masters bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dmac > dtc > cpu (low) an internal bus access by an internal bus master, and external bus release, can be executed in parallel. in the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low) 155 6.8.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dmac and dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a-5, bus states during instruction execution, for timings at which the bus is not transferred. ? if the cpu is in sleep mode, it transfers the bus immediately. dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). dmac: the dmac sends the bus arbiter a request for the bus when an activation request is generated. in the case of an external request in short address mode or normal mode, and in cycle steal mode, the dmac releases the bus after a single transfer. in block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of the transfer. 6.8.4 external bus release usage note external bus release can be performed on completion of an external bus cycle. the cs signal remains low until the end of the external bus cycle. therefore, when external bus release is performed, the cs signal may change from the low level to the high-impedance state. 156 6.9 resets and the bus controller in a power-on reset, the h8s/2214, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. in a manual reset, the bus controllers registers and internal state are maintained, and an executing external bus cycle is completed. in this case, wait input is ignored and write data is not guaranteed. 6.10 external module expansion function 6.10.1 overview the h8s/2214 has an external module expansion function to provide for the addition of peripheral devices. using this function to provide a combination of h8s/2214 and external modules makes it possible to implement a multichip system on the user board. figure 6-21 shows a block diagram. bus access states can be changed by means of a bus controller setting. the exms signal is output to external modules for addresses h'ffff40 to h'ffff5f. priority and dtc activation can be specified for interrupts exirq7 to exirq0 in the same way as for the h8s/2214s on-chip supporting functions. the dtc data transfer end signal for exirq7 to exirq0 interrupt input is output from exdtce . also, the inverse of the value of bit 0 in module stop control register b is output from exmstp. a23 to a0 d15 to d0 exmstp exms exdtce exirq7 to exirq0 h8s/2214 external module figure 6-21 multichip block diagram 157 6.10.2 pin configuration table 6-7 summarizes the pins of the external module expansion function. table 6-7 external module expansion function pins name symbol i/o function external expansion interrupt request 7 to 0 exirq7 to exirq0 input input pins for interrupt requests from external modules external expansion module select exms output select signal for external modules external expansion dtc transfer end exdtce output dtc transfer end signal for exirq7 to exirq0 interrupt input external expansion module stop exmstp output module stop signal for external modules 6.10.3 register configuration table 6-8 summarizes the registers of the bus controller. table 6-8 bus controller registers initial value name abbreviation r/w power-on reset manual reset address * interrupt request input pin select register 0 ipinsel0 r/w h'00 retained h'fe4a external module connection output pin select register opinsel r/w b'-000---- retained h'fe4e module stop control register b mstpcrb r/w h'ff h'ff h'fde9 note: * lower 16 bits of the address. 158 6.11 register descriptions 6.11.1 interrupt request input pin select register 0 (ipinsel0) 7 p36 irq7e 0 r/w 6 p47 irq6e 0 r/w 5 p46 irq5e 0 r/w 4 p44 irq4e 0 r/w 3 p43 irq3e 0 r/w 0 p40 irq0e 0 r/w 2 p42 irq2e 0 r/w 1 p41 irq1e 0 r/w bit initial value r/w : : : ipinsel0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt request input signals ( exirq7 to exirq0 ) from externally connected modules when operating as h8s/2214 modules. ipinsel0 is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state in a manual reset and in software standby mode. bit 7enable of exirq7 input from p36 (p36irq7e): selects whether or not p36 is used as the exirq7 input pin. bit 7 p36irq7e description 0 p36 is not used as exirq7 input (initial value) 1 p36 is used as exirq7 input bit 6enable of exirq6 input from p47 (p47irq6e): selects whether or not p47 is used as the exirq6 input pin. bit 6 p47irq6e description 0 p47 is not used as exirq6 input (initial value) 1 p47 is used as exirq6 input bit 5enable of exirq5 input from p46 (p46irq5e): selects whether or not p46 is used as the exirq5 input pin. bit 5 p46irq5e description 0 p46 is not used as exirq5 input (initial value) 1 p46 is used as exirq5 input 159 bit 4enable of exirq4 input from p44 (p44irq4e): selects whether or not p44 is used as the exirq4 input pin. bit 4 p44irq4e description 0 p44 is not used as exirq4 input (initial value) 1 p44 is used as exirq4 input bit 3enable of exirq3 input from p43 (p43irq3e): selects whether or not p43 is used as the exirq3 input pin. bit 3 p43irq3e description 0 p43 is not used as exirq3 input (initial value) 1 p43 is used as exirq3 input bit 2enable of exirq2 input from p42 (p42irq2e): selects whether or not p42 is used as the exirq2 input pin. bit 2 p42irq2e description 0 p42 is not used as exirq2 input (initial value) 1 p42 is used as exirq2 input bit 1enable of exirq1 input from p41 (p41irq1e): selects whether or not p41 is used as the exirq1 input pin. bit 1 p41irq1e description 0 p41 is not used as exirq1 input (initial value) 1 p41 is used as exirq1 input bit 0enable of exirq0 input from p40 (p40irq0e): selects whether or not p40 is used as the exirq0 input pin. bit 0 p40irq0e description 0 p40 is not used as exirq0 input (initial value) 1 p40 is used as exirq0 input 160 6.11.2 external module connection output pin select register (opinsel) 7 undefined r/w 6 p76 stpoe 0 r/w 5 p75 msoe 0 r/w 4 p74 dtcoe 0 r/w 3 undefined 0 undefined 2 undefined 1 undefined bit initial value r/w : : : opinsel is an 8-bit readable/writable register that selects whether or not output signals (exdtcen, exmstp, exmsn) to externally connected modules are output to pins p77 to p74 in h8s/2214 operation. opinsel bits 6 to 4 are initialized to 000 by a power-on reset and in hardware standby mode. they retain their previous states in a manual reset and in software standby mode. bit 7reserved: this bit will return an undefined value if read, and should only be written with 0. bit 6enable of exmstp output to p76 (p76stpoe): selects whether or not the exmstp module stop signal to external modules (corresponding to bit 0 in mstpcrb) is output to p76. bit 6 p76stpoe description 0 exmstp is not output to p76 (initial value) 1 exmstp is output to p76 bit 5enable of exms output to p75 (p75msoe): selects whether or not the exms module stop signal to external modules (corresponding to addresses h'ffff40 to h'ffff5f) is output to p75. bit 5 p75msoe description 0 exms is not output to p75 (initial value) 1 exms is output to p75 161 bit 4enable of exdtce output to p74 (p74dtcoe): selects whether or not the exdtce signal, indicating that dtc transfer corresponding to exirq0f input is in progress, is output to p74. this signal is used, for example, when the dtc in the chip has been activated by an interrupt (exirq0 to exirqf) from an external module, and the interrupt request is to be cleared automatically on the external module side by dtc transfer. bit 4 p74dtcoe description 0 exdtce is not output to p74 (initial value) 1 exdtce is output to p74 bits 3 to 0reserved: these bits will return an undefined value if read, and should only be written with 0. 6.11.3 module stop control register b (mstpcrb) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w : : : mstpcrb is an 8-bit readable/writable register that performs module stop mode control. when the mstpb0 bit is set to 1, the external module expansion function stops operation at the end of the bus cycle, and enters module stop mode. for details, see section 17.5, module stop mode. mstpcrb is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 0module stop (mstpb0): specifies the external module expansion function module stop mode. bit 0 mstpb0 description 0 external module expansion function module stop mode is cleared 1 external module expansion function module stop mode is set (initial value) 162 6.12 basic timing figure 6-22 shows the timing of external module area (h'ffff40 to h'ffff5f) dtc data transfer using 3-state access. t 1 t 2 t 3 t 1 t 2 t 3 exms exdtce rd t 1 t 2 t 3 t 1 t 2 t 3 external module area read write ? address exms exdtce wr ? address (a) timing of external module area read by dtc read external module area write (b) timing of external module area write by dtc figure 6-22 timing of external module area access by dtc 163 section 7 dma controller 7.1 overview the h8s/2214 has a built-in dma controller (dmac) which can carry out data transfer on up to 4 channels. 7.1.1 features the features of the dmac are listed below. ? choice of short address mode or full address mode short address mode ? maximum of 4 channels can be used ? choice of dual address mode ? in dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits ? choice of sequential mode, idle mode, or repeat mode for dual address mode full address mode ? maximum of 2 channels can be used ? transfer source and transfer destination address specified as 24 bits ? choice of normal mode or block transfer mode ? 16-mbyte address space can be specified directly ? byte or word can be set as the transfer unit ? activation sources: internal interrupt, external request, auto-request (depending on transfer mode) ? three 16-bit timer-pulse unit (tpu) compare match/input capture interrupts ? serial communication interface (sci0, sci1) transmission complete interrupt, reception complete interrupt ? external request ? auto-request ? module stop mode can be set ? the initial setting enables dmac registers to be accessed. dmac operation is halted by setting module stop mode 164 7.1.2 block diagram a block diagram of the dmac is shown in figure 7-1. internal address bus address buffer processor internal interrupts tgi0a tgi1a tgi2a txi0 rxi0 txi1 rxi1 external pins dreq0 dreq1 tend0 tend1 interrupt signals dend0a dend0b dend1a dend1b control logic dmawer dmacr1b dmacr1a dmacr0b dmacr0a dmatcr dmabcr data buffer internal data bus mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b legend : dma write enable register : dma terminal control register : dma band control register (for all channels) : dma control register : memory address register : i/o address register : executive transfer counter register channel 0 channel 1 channel 0a channel 0b channel 1a channel 1b module data bus dmawer dmatcr dmabcr dmacr mar ioar etcr figure 7-1 block diagram of dmac 165 7.1.3 overview of functions tables 7-1 and 7-2 summarize dmac functions in short address mode and full address mode, respectively. table 7-1 overview of dmac functions (short address mode) address register bit length transfer mode transfer source source destination dual address mode ? sequential mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address incremented/decremented by 1 or 2 ? 1 to 65536 transfers ? idle mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address fixed ? 1 to 65536 transfers ? repeat mode ? 1-byte or 1-word transfer executed for one transfer request ? memory address incremented/ decremented by 1 or 2 ? after specified number of transfers (1 to 256), initial state is restored and operation continues ? tpu channel 0 to 2 compare match/input capture a interrupt ? sci transmission complete interrupt ? sci reception complete interrupt ? external request 24/16 16/24 166 table 7-2 overview of dmac functions (full address mode) address register bit length transfer mode transfer source source destination ? normal mode auto-request ? transfer request retained internally ? transfers continue for the specified number of times (1 to 65536) ? choice of burst or cycle steal transfer ? auto-request 24 24 external request ? 1-byte or 1-word transfer executed for one transfer request ? 1 to 65536 transfers ? external request ? block transfer mode ? specified block size transfer executed for one transfer request ? 1 to 65536 transfers ? either source or destination specifiable as block area ? block size: 1 to 256 bytes or words ? tpu channel 0 to 2 compare match/input capture a interrupt ? sci transmission complete interrupt ? sci reception complete interrupt ? external request 24 24 167 7.1.4 pin configuration table 7-3 summarizes the dmac pins. in short address mode, external request transfer, and transfer end output are not performed for channel a. when the dreq pin is used, do not designate the corresponding port for output. with regard to the tend pins, whether or not the corresponding port is used as a tend pin can be specified by means of a register setting. table 7-3 dmac pins channel pin name symbol i/o function 0 dma request 0 dreq0 input dmac channel 0 external request dma transfer end 0 tend0 output dmac channel 0 transfer end 1 dma request 1 dreq1 input dmac channel 1 external request dma transfer end 1 tend1 output dmac channel 1 transfer end 168 7.1.5 register configuration table 7-4 summarizes the dmac registers. table 7-4 dmac registers channel name abbreviation r/w initial value address * bus width 0 memory address register 0a mar0a r/w undefined h'fee0 16 bits i/o address register 0a ioar0a r/w undefined h'fee4 16 bits transfer count register 0a etcr0a r/w undefined h'fee6 16 bits memory address register 0b mar0b r/w undefined h'fee8 16 bits i/o address register 0b ioar0b r/w undefined h'feec 16 bits transfer count register 0b etcr0b r/w undefined h'feee 16 bits 1 memory address register 1a mar1a r/w undefined h'fef0 16 bits i/o address register 1a ioar1a r/w undefined h'fef4 16 bits transfer count register 1a etcr1a r/w undefined h'fef6 16 bits memory address register 1b mar1b r/w undefined h'fef8 16 bits i/o address register 1b ioar1b r/w undefined h'fefc 16 bits transfer count register 1b etcr1b r/w undefined h'fefe 16 bits 0, 1 dma write enable register dmawer r/w h'00 h'ff60 8 bits dma terminal control register dmatcr r/w h'00 h'ff61 8 bits dma control register 0a dmacr0a r/w h'00 h'ff62 16 bits dma control register 0b dmacr0b r/w h'00 h'ff63 16 bits dma control register 1a dmacr1a r/w h'00 h'ff64 16 bits dma control register 1b dmacr1b r/w h'00 h'ff65 16 bits dma band control register dmabcr r/w h'0000 h'ff66 16 bits module stop control register a mstpcra r/w h'3f h'fde8 8 bits note: * lower 16 bits of the address. 169 7.2 register descriptions (1) (short address mode) short address mode transfer can be performed for channels a and b independently. short address mode transfer is specified for each channel by clearing the fae bit in dmabcr to 0, as shown in table 7-5. short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits fae1 and fae0. table 7-5 short address mode and full address mode (for 1 channel: example of channel 0) fae0 description 0 short address mode specified (channels a and b operate independently) channel 0a mar0a specifies transfer source/transfer destination address specifies transfer destination/transfer source address specifies number of transfers specifies transfer size, mode, activation source, etc. specifies transfer source/transfer destination address specifies transfer destination/transfer source address specifies number of transfers specifies transfer size, mode, activation source, etc. ioar0a etcr0a dmacr0a channel 0b mar0b ioar0b etcr0b dmacr0b 1 full address mode specified (channels a and b operate in combination) channel 0 mar0a specifies transfer source address specifies transfer destination address not used not used specifies number of transfers specifies number of transfers (used in block transfer mode only) specifies transfer size, mode, activation source, etc. ioar0a etcr0a dmacr0a mar0b ioar0b etcr0b dmacr0b 170 7.2.1 memory address registers (mar) bit :31302928272625242322212019181716 mar : initial value : 0 0 0 00000 ******** r/w :r/wr/wr/wr/wr/wr/wr/wr/w bit :1514131211109876543210 mar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined mar is a 32-bit readable/writable register that specifies the transfer source address or destination address. the upper 8 bits of mar are reserved: they are always read as 0, and cannot be modified. whether mar functions as the source address register or as the destination address register can be selected by means of the dtdir bit in dmacr. mar is incremented or decremented each time a byte or word transfer is executed, so that the address specified by mar is constantly updated. for details, see section 7.2.4, dma control register (dmacr). mar is not initialized by a reset or in standby mode. 171 7.2.2 i/o address register (ioar) bit :1514131211109876543210 ioar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined ioar is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. the upper 8 bits of the transfer address are automatically set to h'ff. whether ioar functions as the source address register or as the destination address register can be selected by means of the dtdir bit in dmacr. ioar is invalid in single address mode. ioar is not incremented or decremented each time a transfer is executed, so that the address specified by ioar is fixed. ioar is not initialized by a reset or in standby mode. 7.2.3 execute transfer count register (etcr) etcr is a 16-bit readable/writable register that specifies the number of transfers. the setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) sequential mode and idle mode transfer counter bit :1514131211109876543210 etcr : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined in sequential mode and idle mode, etcr functions as a 16-bit transfer counter (with a count range of 1 to 65536). etcr is decremented by 1 each time a transfer is performed, and when the count reaches h'0000, the dte bit in dmabcr is cleared, and transfer ends. 172 (2) repeat mode transfer number storage bit :151413121110 9 8 etcrh : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w transfer counter bit:7 65 43 21 0 etcrl : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w * : undefined in repeat mode, etcr functions as transfer counter etcrl (with a count range of 1 to 256) and transfer number storage register etcrh. etcrl is decremented by 1 each time a transfer is performed, and when the count reaches h'00, etcrl is loaded with the value in etcrh. at this point, mar is automatically restored to the value it had when the count was started. the dte bit in dmabcr is not cleared, and so transfers can be performed repeatedly until the dte bit is cleared by the user. etcr is not initialized by a reset or in standby mode. 7.2.4 dma control register (dmacr) bit:7 65 43 21 0 dmacr : dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmacr is an 8-bit readable/writable register that controls the operation of each dmac channel. dmacr is initialized to h'00 by a reset, and in standby mode. 173 bit 7data transfer size (dtsz): selects the size of data to be transferred at one time. bit 7 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 6data transfer increment/decrement (dtid): selects incrementing or decrementing of mar every data transfer in sequential mode or repeat mode. in idle mode, mar is neither incremented nor decremented. bit 6 dtid description 0 mar is incremented after a data transfer (initial value) ? when dtsz = 0, mar is incremented by 1 after a transfer ? when dtsz = 1, mar is incremented by 2 after a transfer 1 mar is decremented after a data transfer ? when dtsz = 0, mar is decremented by 1 after a transfer ? when dtsz = 1, mar is decremented by 2 after a transfer bit 5repeat enable (rpe): used in combination with the dtie bit in dmabcr to select the mode (sequential, idle, or repeat) in which transfer is to be performed. bit 5 dmabcr rpe dtie description 0 0 transfer in sequential mode (no transfer end interrupt) (initial value) 1 transfer in sequential mode (with transfer end interrupt) 1 0 transfer in repeat mode (no transfer end interrupt) 1 transfer in idle mode (with transfer end interrupt) for details of operation in sequential, idle, and repeat mode, see section 7.5.2, sequential mode, section 7.5.3, idle mode, and section 7.5.4, repeat mode. bit 4data transfer direction (dtdir): to specify the data transfer direction (source or destination). 174 bit 4 dtdir description 0 transfer with mar as source address and ioar as destination address initial value) 1 transfer with ioar as source address and mar as destination address bits 3 to 0data transfer factor (dtf3 to dtf0): these bits select the data transfer factor (activation source). there are some differences in activation sources for channel a and for channel b. channel a bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0000 (initial value) 1 10 1 1 0 0 activated by sci channel 0 transmission complete interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmission complete interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 100 1 10 1 175 channel b bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0000 (initial value) 1 1 0 activated by dreq pin falling edge input * 1 activated by dreq pin low-level input 1 0 0 activated by sci channel 0 transmission complete interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmission complete interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 100 1 10 1 note: * detected as a low level in the first transfer after transfer is enabled. the same factor can be selected for more than one channel. in this case, activation starts with the highest-priority channel according to the relative channel priorities. for relative channel priorities, see section 7.5.13, dmac multi-channel operation. 176 7.2.5 dma band control register (dmabcr) bit :151413121110 9 8 dmabcrh : fae1 fae0 dta1b dta1a dta0b dta0a initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bit:7 65 43 21 0 dmabcrl : dte1b dte1a dte0b dte0a dtie1b dtie1a dtie0b dtie0a initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmabcr is a 16-bit readable/writable register that controls the operation of each dmac channel. dmabcr is initialized to h'0000 by a reset, and in standby mode. bit 15full address enable 1 (fae1): specifies whether channel 1 is to be used in short address mode or full address mode. in short address mode, channels 1a and 1b are used as independent channels. bit 15 fae1 description 0 short address mode (initial value) 1 full address mode bit 14full address enable 0 (fae0): specifies whether channel 0 is to be used in short address mode or full address mode. in short address mode, channels 0a and 0b are used as independent channels. bit 14 fae0 description 0 short address mode (initial value) 1 full address mode bit 13 and 12reserved: this bit is reserved and only 0 can be written to, writing 1 causes a malfunction error. 177 bits 11 to 8data transfer acknowledge (dta): these bits enable or disable clearing, when dma transfer is performed, of the internal interrupt source selected by the data transfer factor setting. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by dma transfer. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the cpu or dtc. when dte = 1 and dta = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the cpu or dtc in parallel. in this case, the interrupt source should be cleared by the cpu or dtc transfer. when dte = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the cpu or dtc regardless of the dta bit setting. bit 11data transfer acknowledge 1b (dta1b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1b data transfer factor setting. bit 11 dta1b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 10data transfer acknowledge 1a (dta1a): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1a data transfer factor setting. bit 10 dta1a description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled 178 bit 9data transfer acknowledge 0b (dta0b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0b data transfer factor setting. bit 9 dta0b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 8data transfer acknowledge 0a (dta0a): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0a data transfer factor setting. bit 8 dta0a description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bits 7 to 4data transfer enable (dte): when dte = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. if the activation source is an internal interrupt, an interrupt request is issued to the cpu or dtc. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. the conditions for the dte bit being cleared to 0 are as follows: ? when initialization is performed ? when the specified number of transfers have been completed in a transfer mode other than repeat mode ? when 0 is written to the dte bit to forcibly abort the transfer, or for a similar reason when dte = 1, data transfer is enabled and the dmac waits for a request by the activation source selected by the data transfer factor setting. when a request is issued by the activation source, dma transfer is executed. the condition for the dte bit being set to 1 is as follows: ? when 1 is written to the dte bit after the dte bit is read as 0 179 bit 7data transfer enable 1b (dte1b): enables or disables data transfer on channel 1b. bit 7 dte1b description 0 data transfer disabled (initial value) 1 data transfer enabled bit 6data transfer enable 1a (dte1a): enables or disables data transfer on channel 1a. bit 6 dte1a description 0 data transfer disabled (initial value) 1 data transfer enabled bit 5data transfer enable 0b (dte0b): enables or disables data transfer on channel 0b. bit 5 dte0b description 0 data transfer disabled (initial value) 1 data transfer enabled bit 4data transfer enable 0a (dte0a): enables or disables data transfer on channel 0a. bit 4 dte0a description 0 data transfer disabled (initial value) 1 data transfer enabled bits 3 to 0data transfer end interrupt enable (dtie): these bits enable or disable an interrupt to the cpu or dtc when transfer ends. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. a transfer end interrupt can be canceled either by clearing the dtie bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the dte bit to 1. 180 bit 3data transfer interrupt enable 1b (dtie1b): enables or disables the channel 1b transfer end interrupt. bit 3 dtie1b description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 2data transfer interrupt enable 1a (dtie1a): enables or disables the channel 1a transfer end interrupt. bit 2 dtie1a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 1data transfer interrupt enable 0b (dtie0b): enables or disables the channel 0b transfer end interrupt. bit 1 dtie0b description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 0data transfer interrupt enable 0a (dtie0a): enables or disables the channel 0a transfer end interrupt. bit 0 dtie0a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled 181 7.3 register descriptions (2) (full address mode) full address mode transfer is performed with channels a and b together. for details of full address mode setting, see table 7-5. 7.3.1 memory address register (mar) bit :31302928272625242322212019181716 mar : initial value : 0 0 0 00000 ******** r/w :r/wr/wr/wr/wr/wr/wr/wr/w bit :1514131211109876543210 mar : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined mar is a 32-bit readable/writable register; mara functions as the transfer source address register, and marb as the destination address register. mar is composed of two 16-bit registers, marh and marl. the upper 8 bits of marh are reserved: they are always read as 0, and cannot be modified. mar is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. for details, see section 7.3.4, dma control register (dmacr). mar is not initialized by a reset or in standby mode. 7.3.2 i/o address register (ioar) ioar is not used in full address transfer. 182 7.3.3 execute transfer count register (etcr) etcr is a 16-bit readable/writable register that specifies the number of transfers. the function of this register is different in normal mode and in block transfer mode. etcr is not initialized by a reset or in standby mode. (1) normal mode etcra transfer counter bit :1514131211109876543210 etcr : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w * : undefined in normal mode, etcra functions as a 16-bit transfer counter. etcra is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches h'0000. etcrb is not used at this time. etcrb etcrb is not used in normal mode. (2) block transfer mode etcra holds block size bit :151413121110 9 8 etcrah : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w block size counter bit:7 65 43 21 0 etcral : initial value : ******** r/w : r/w r/w r/w r/w r/w r/w r/w r/w * : undefined 183 etcrb block transfer counter bit :1514131211109876543210 etcrb : initial value : **************** r/w : r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w in block transfer mode, etcral functions as an 8-bit block size counter and etcrah holds the block size. etcral is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches h'00, etcral is loaded with the value in etcrah. so by setting the block size in etcrah and etcral, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. etcrb functions in block transfer mode, as a 16-bit block transfer counter. etcrb is decremented by 1 each time a block is transferred, and transfer ends when the count reaches h'0000. 7.3.4 dma control register (dmacr) dmacr is a 16-bit readable/writable register that controls the operation of each dmac channel. in full address mode, dmacra and dmacrb have different functions. dmacr is initialized to h'0000 by a reset, and in standby mode. dmacra bit :151413121110 9 8 dmacra : dtsz said saide blkdir blke initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmacrb bit:7 65 43 21 0 dmacrb : daid daide dtf3 dtf2 dtf1 dtf0 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w 184 bit 15data transfer size (dtsz): selects the size of data to be transferred at one time. bit 15 dtsz description 0 byte-size transfer (initial value) 1 word-size transfer bit 14source address increment/decrement (said) bit 13source address increment/decrement enable (saide): these bits specify whether source address register mara is to be incremented, decremented, or left unchanged, when data transfer is performed. bit 14 bit 13 said saide description 0 0 mara is fixed (initial value) 1 mara is incremented after a data transfer ? when dtsz = 0, mara is incremented by 1 after a transfer ? when dtsz = 1, mara is incremented by 2 after a transfer 1 0 mara is fixed 1 mara is decremented after a data transfer ? when dtsz = 0, mara is decremented by 1 after a transfer ? when dtsz = 1, mara is decremented by 2 after a transfer bit 12block direction (blkdir) bit 11block enable (blke): these bits specify whether normal mode or block transfer mode is to be used. if block transfer mode is specified, the blkdir bit specifies whether the source side or the destination side is to be the block area. bit 12 bit 11 blkdir blke description 0 0 transfer in normal mode (initial value) 1 transfer in block transfer mode, destination side is block area 1 0 transfer in normal mode 1 transfer in block transfer mode, source side is block area for operation in normal mode and block transfer mode, see section 7.5, operation. 185 bits 10 to 7reserved: can be read or written to. bit 6destination address increment/decrement (daid) bit 5destination address increment/decrement enable (daide): these bits specify whether destination address register marb is to be incremented, decremented, or left unchanged, when data transfer is performed. bit 6 bit 5 daid daide description 0 0 marb is fixed (initial value) 1 marb is incremented after a data transfer ? when dtsz = 0, marb is incremented by 1 after a transfer ? when dtsz = 1, marb is incremented by 2 after a transfer 1 0 marb is fixed 1 marb is decremented after a data transfer ? when dtsz = 0, marb is decremented by 1 after a transfer ? when dtsz = 1, marb is decremented by 2 after a transfer bit 4reserved: can be read or written to. bits 3 to 0data transfer factor (dtf3 to dtf0): these bits select the data transfer factor (activation source). the factors that can be specified differ between normal mode and block transfer mode. ? normal mode bit 3 bit 2 bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0000 (initial value) 1 1 0 activated by dreq pin falling edge input 1 activated by dreq pin low-level input 10 * 1 0 auto-request (cycle steal) 1 auto-request (burst) 1 *** * : don't care 186 ? block transfer mode bit 3 bit bit 1 bit 0 dtf3 dtf2 dtf1 dtf0 description 0000 (initial value) 1 1 0 activated by dreq pin falling edge input * 1 activated by dreq pin low-level input 1 0 0 activated by sci channel 0 transmission complete interrupt 1 activated by sci channel 0 reception complete interrupt 1 0 activated by sci channel 1 transmission complete interrupt 1 activated by sci channel 1 reception complete interrupt 1000 activated by tpu channel 0 compare match/input capture a interrupt 1 activated by tpu channel 1 compare match/input capture a interrupt 1 0 activated by tpu channel 2 compare match/input capture a interrupt 1 100 1 10 1 note: * detected as a low level in the first transfer after transfer is enabled. the same factor can be selected for more than one channel. in this case, activation starts with the highest-priority channel according to the relative channel priorities. for relative channel priorities, see section 7.5.13, dmac multi-channel operation. 187 7.3.5 dma band control register (dmabcr) bit :151413121110 9 8 dmabcrh : fae1 fae0 dta1b dta1a dta0b dta0a initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w bit:7 65 43 21 0 dmabcrl : dtme1 dte1 dtme0 dte0 dtie1b dtie1a dtie0b dtie0a initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w dmabcr is a 16-bit readable/writable register that controls the operation of each dmac channel. dmabcr is initialized to h'0000 by a reset, and in standby mode. bit 15full address enable 1 (fae1): specifies whether channel 1 is to be used in short address mode or full address mode. in full address mode, channels 1a and 1b are used together as a single channel. bit 15 fae1 description 0 short address mode (initial value) 1 full address mode bit 14full address enable 0 (fae0): specifies whether channel 0 is to be used in short address mode or full address mode. in full address mode, channels 0a and 0b are used together as a single channel. bit 14 fae0 description 0 short address mode (initial value) 1 full address mode 188 bits 13 and 12reserved: this bit is reserved and only 0 can be written to, writing 1 causes a malfunction error. bits 11 and 9data transfer acknowledge (dta): these bits enable or disable clearing, when dma transfer is performed, of the internal interrupt source selected by the data transfer factor setting. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by dma transfer. when dte = 1 and dta = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the cpu or dtc. when the dte = 1 and the dta = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the cpu or dtc in parallel. in this case, the interrupt source should be cleared by the cpu or dtc transfer. when the dte = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the cpu or dtc regardless of the dta bit setting. the state of the dtme bit does not affect the above operations. bit 11data transfer acknowledge 1 (dta1b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. bit 11 dta1b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled bit 9data transfer acknowledge 0 (dta0b): enables or disables clearing, when dma transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. bit 9 dta0b description 0 clearing of selected internal interrupt source at time of dma transfer is disabled (initial value) 1 clearing of selected internal interrupt source at time of dma transfer is enabled 189 bits 10 and 8reserved (dta1a, dta0a): reserved bits in full address mode. read and write possible. bits 7 and 5data transfer master enable (dtme): together with the dte bit, these bits control enabling or disabling of data transfer on the relevant channel. when both the dtme bit and the dte bit are set to 1, transfer is enabled for the channel. if the relevant channel is in the middle of a burst mode transfer when an nmi interrupt is generated, the dtme bit is cleared, the transfer is interrupted, and bus mastership passes to the cpu. when the dtme bit is subsequently set to 1 again, the interrupted transfer is resumed. in block transfer mode, however, the dtme bit is not cleared by an nmi interrupt, and transfer is not interrupted. the conditions for the dtme bit being cleared to 0 are as follows: ? when initialization is performed ? when nmi is input in burst mode ? when 0 is written to the dtme bit the condition for dtme being set to 1 is as follows: ? when 1 is written to dtme after dtme is read as 0 bit 7data transfer master enable 1 (dtme1): enables or disables data transfer on channel 1. bit 7 dtme1 description 0 data transfer disabled. in burst mode, cleared to 0 by an nmi interrupt (initial value) 1 data transfer enabled bit 5data transfer master enable 0 (dtme0): enables or disables data transfer on channel 0. bit 5 dtme0 description 0 data transfer disabled. in normal mode, cleared to 0 by an nmi interrupt (initial value) 1 data transfer enabled 190 bits 6 and 4data transfer enable (dte): when dte = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. if the activation source is an internal interrupt, an interrupt request is issued to the cpu or dtc. if the dtie bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu. the conditions for the dte bit being cleared to 0 are as follows: ? when initialization is performed ? when the specified number of transfers have been completed ? when 0 is written to the dte bit to forcibly abort the transfer, or for a similar reason when dte = 1 and dtme = 1, data transfer is enabled and the dmac waits for a request by the activation source selected by the data transfer factor setting. when a request is issued by the activation source, dma transfer is executed. the condition for the dte bit being set to 1 is as follows: ? when 1 is written to the dte bit after the dte bit is read as 0 bit 6data transfer enable 1 (dte1): enables or disables data transfer on channel 1. bit 6 dte1 description 0 data transfer disabled (initial value) 1 data transfer enabled bit 4data transfer enable 0 (dte0): enables or disables data transfer on channel 0. bit 4 dte0 description 0 data transfer disabled (initial value) 1 data transfer enabled bits 3 and 1data transfer interrupt enable b (dtieb): these bits enable or disable an interrupt to the cpu or dtc when transfer is interrupted. if the dtieb bit is set to 1 when dtme = 0, the dmac regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the cpu or dtc. a transfer break interrupt can be canceled either by clearing the dtieb bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the dtme bit to 1. 191 bit 3data transfer interrupt enable 1b (dtie1b): enables or disables the channel 1 transfer break interrupt. bit 3 dtie1b description 0 transfer break interrupt disabled (initial value) 1 transfer break interrupt enabled bit 1data transfer interrupt enable 0b (dtie0b): enables or disables the channel 0 transfer break interrupt. bit 1 dtie0b description 0 transfer break interrupt disabled (initial value) 1 transfer break interrupt enabled bits 2 and 0data transfer end interrupt enable a (dtiea): these bits enable or disable an interrupt to the cpu or dtc when transfer ends. if dtiea bit is set to 1 when dte = 0, the dmac regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the cpu or dtc. a transfer end interrupt can be canceled either by clearing the dtiea bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the dte bit to 1. bit 2data transfer interrupt enable 1a (dtie1a): enables or disables the channel 1 transfer end interrupt. bit 2 dtie1a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled bit 0data transfer interrupt enable 0a (dtie0a): enables or disables the channel 0 transfer end interrupt. bit 0 dtie0a description 0 transfer end interrupt disabled (initial value) 1 transfer end interrupt enabled 192 7.4 register descriptions (3) 7.4.1 dma write enable register (dmawer) the dmac can activate the dtc with a transfer end interrupt, rewrite the channel on which the transfer ended using a dtc chain transfer, and reactivate the dtc. dmawer applies restrictions so that only specific bits of dmacr for the specific channel and also dmatcr and dmabcr can be changed to prevent inadvertent changes being made to registers other than those for the channel concerned. the restrictions applied by dmawer are valid for the dtc. figure 7-2 shows the transfer areas for activating the dtc with a channel 0a transfer end interrupt, and reactivating channel 0a. the address register and count register area is re-set by the first dtc transfer, then the control register area is re-set by the second dtc chain transfer. when re-setting the control register area, perform masking by setting bits in dmawer to prevent modification of the contents of the other channels. dtc mar0a ioar0a etcr0a mar0b ioar0b etcr0b mar1a ioar1a etcr1a mar1b ioar1b etcr1b dmatcr dmacr0b dmacr1b dmawer dmacr0a dmacr1a dmabcr second transfer area using chain transfer first transfer area figure 7-2 areas for register re-setting by dtc (example: channel 0a) 193 bit:7 65 43 21 0 dmawer : we1b we1a we0b we0a initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w dmawer is an 8-bit readable/writable register that controls enabling or disabling of writes to the dmacr, dmabcr, and dmatcr by the dtc. dmawer is initialized to h'00 by a reset, and in standby mode. bits 7 to 4reserved: read-only bits, always read as 0. bit 3write enable 1b (we1b): enables or disables writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr by the dtc. bit 3 we1b description 0 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are disabled (initial value) 1 writes to all bits in dmacr1b, bits 11, 7, and 3 in dmabcr, and bit 5 in dmatcr are enabled bit 2write enable 1a (we1a): enables or disables writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr by the dtc. bit 2 we1a description 0 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are disabled (initial value) 1 writes to all bits in dmacr1a, and bits 10, 6, and 2 in dmabcr are enabled bit 1write enable 0b (we0b): enables or disables writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr. bit 1 we0b description 0 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are disabled (initial value) 1 writes to all bits in dmacr0b, bits 9, 5, and 1 in dmabcr, and bit 4 in dmatcr are enabled 194 bit 0write enable 0a (we0a): enables or disables writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr. bit 0 we0a description 0 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are disabled (initial value) 1 writes to all bits in dmacr0a, and bits 8, 4, and 0 in dmabcr are enabled writes by the dtc to bits 15 to 12 (fae and sae) in dmabcr are invalid regardless of the dmawer settings. these bits should be changed, if necessary, by cpu processing. in writes by the dtc to bits 7 to 4 (dte) in dmabcr, 1 can be written without first reading 0. to reactivate a channel set to full address mode, write 1 to both write enable a and write enable b for the channel to be reactivated. mar, ioar, and etcr are always write-enabled regardless of the dmawer settings. when modifying these registers, the channel for which the modification is to be made should be halted. 7.4.2 dma terminal control register (dmatcr) bit:7 65 43 21 0 dmatcr : tee1 tee0 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w dmatcr is an 8-bit readable/writable register that controls enabling or disabling of dmac transfer end pin output. a port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. dmatcr is initialized to h'00 by a reset, and in standby mode. bits 7 and 6reserved: read-only bits, always read as 0. bit 5transfer end enable 1 (tee1): enables or disables transfer end pin 1 ( tend1 ) output. bit 5 tee1 description 0 tend1 pin output disabled (initial value) 1 tend1 pin output enabled 195 bit 4transfer end enable 0 (tee0): enables or disables transfer end pin 0 ( tend0 ) output. bit 4 tee0 description 0 tend0 pin output disabled (initial value) 1 tend0 pin output enabled the tend pins are assigned only to channel b in short address mode. the transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. an exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. bits 3 to 0reserved: read-only bits, always read as 0. 7.4.3 module stop control register a (mstpcra) bit:7 65 43 21 0 mstpa7 mstpa6 mstpa5 mstpa4 mstpa3 mstpa2 mstpa1 mstpa0 initial value : 0 0 1 1 1 1 1 1 r/w : r/w r/w r/w r/w r/w r/w r/w r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa7 bit in mstpcr is set to 1, the dmac operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 17.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. bit 7module stop (mstp7): specifies the dmac module stop mode. bits 7 mstpa7 description 0 dmac module stop mode cleared (initial value) 1 dmac module stop mode set 196 7.5 operation 7.5.1 transfer modes table 7-6 lists the dmac modes. table 7-6 dmac transfer modes transfer mode transfer source remarks short address mode dual address mode (1) sequential mode (2) idle mode (3) repeat mode ? tpu channel 0 to 2 compare match/input capture a interrupt ? sci transmission complete interrupt ? sci reception complete interrupt ? external request ? up to 4 channels can operate independently ? external request applies to channel b only full address mode (4) normal mode ? external request ? auto-request ? max. 2-channel operation, combining channels a and b (5) block transfer mode ? tpu channel 0 to 2 compare match/input capture a interrupt ? sci transmission complete interrupt ? sci reception complete interrupt ? external request ? with auto-request, burst mode transfer or cycle steal transfer can be selected 197 operation in each mode is summarized below. (1) sequential mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. one address is specified as 24 bits, and the other as 16 bits. the transfer direction is programmable. (2) idle mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. one address is specified as 24 bits, and the other as 16 bits. the transfer source address and transfer destination address are fixed. the transfer direction is programmable. (3) repeat mode in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. when the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. no interrupt request is sent to the cpu or dtc. one address is specified as 24 bits, and the other as 16 bits. the transfer direction is programmable. (4) normal mode ? auto-request by means of register settings only, the dmac is activated, and transfer continues until the specified number of transfers have been completed. an interrupt request can be sent to the cpu or dtc when transfer is completed. both addresses are specified as 24 bits. ? cycle steal mode: the bus is released to another bus master every byte or word transfer. ? burst mode: the bus is held and transfer continued until the specified number of transfers have been completed. ? external request in response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. an interrupt request can be sent to the cpu or dtc when the specified number of transfers have been completed. both addresses are specified as 24 bits. (5) block transfer mode in response to a single transfer request, a block transfer of the specified block size is carried out. this is repeated the specified number of times, once each time there is a transfer request. at the end of each single block transfer, one address is restored to its original setting. an interrupt request can be sent to the cpu or dtc when the specified number of block transfers have been completed. both addresses are specified as 24 bits. 198 7.5.2 sequential mode sequential mode can be specified by clearing the rpe bit in dmacr to 0. in sequential mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcr. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 7-7 summarizes register functions in sequential mode. table 7-7 register functions in sequential mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source incremented/ decremented every transfer 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 15 etcr transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend mar : memory address register ioar : i/o address register etcr : transfer count register dtdir : data transfer direction bit mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is incremented or decremented by 1 or 2 each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff. 199 figure 7-3 illustrates operation in sequential mode. address t address b transfer ioar 1 byte or word transfer performed in response to 1 transfer request legend address t = l address b = l + (C1) dtid ? (2 dtsz ? (nC1)) where : l = value set in mar n = value set in etcr figure 7-3 operation in sequential mode the number of transfers is specified as 16 bits in etcr. etcr is decremented by 1 each time a transfer is executed, and when its value reaches h'0000, the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcr, is 65,536. transfer requests (activation sources) consist of external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 2 compare match/input capture a interrupts. external requests can be set for channel b only. 200 figure 7-4 shows an example of the setting procedure for sequential mode. sequential mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl sequential mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. ? clear the fae bit to 0 to select short address mode. ? specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in etcr. [4] set each bit in dmacr. ? set the transfer data size with the dtsz bit. ? specify whether mar is to be incremented or decremented with the dtid bit. ? clear the rpe bit to 0 to select sequential mode. ? specify the transfer direction with the dtdir bit. ? select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. ? specify enabling or disabling of transfer end interrupts with the dtie bit. ? set the dte bit to 1 to enable transfer. figure 7-4 example of sequential mode setting procedure 201 7.5.3 idle mode idle mode can be specified by setting the rpe bit and dtie bit in dmacr to 1. in idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in etcr. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 7-8 summarizes register functions in idle mode. table 7-8 register functions in idle mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source fixed 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 15 etcr transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend mar : memory address register ioar : i/o address register etcr : transfer count register dtdir : data transfer direction bit mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is neither incremented nor decremented each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff. 202 figure 7-5 illustrates operation in idle mode. transfer ioar 1 byte or word transfer performed in response to 1 transfer request mar figure 7-5 operation in idle mode the number of transfers is specified as 16 bits in etcr. etcr is decremented by 1 each time a transfer is executed, and when its value reaches h'0000, the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcr, is 65,536. transfer requests (activation sources) consist of external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 2 compare match/input capture a interrupts. external requests can be set for channel b only. when the dmac is used in single address mode, only channel b can be set. 203 figure 7-6 shows an example of the setting procedure for idle mode. idle mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl idle mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. ? clear the fae bit to 0 to select short address mode. ? specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in etcr. [4] set each bit in dmacr. ? set the transfer data size with the dtsz bit. ? specify whether mar is to be incremented or decremented with the dtid bit. ? set the rpe bit to 1. ? specify the transfer direction with the dtdir bit. ? select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. ? set the dtie bit to 1. ? set the dte bit to 1 to enable transfer. figure 7-6 example of idle mode setting procedure 204 7.5.4 repeat mode repeat mode can be specified by setting the rpe bit in dmacr to 1, and clearing the dtie bit to 0. in repeat mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcr. on completion of the specified number of transfers, mar and etcrl are automatically restored to their original settings and operation continues. one address is specified by mar, and the other by ioar. the transfer direction can be specified by the dtdir bit in dmacr. table 7-9 summarizes register functions in repeat mode. table 7-9 register functions in repeat mode function register dtdir = 0 dtdir = 1 initial setting operation 23 0 mar source address register destination address register start address of transfer destination or transfer source incremented/ decremented every transfer. initial setting is restored when value reaches h'0000 23 0 ioar 15 h'ff destination address register source address register start address of transfer source or transfer destination fixed 0 etcrh 7 0 etcrl 7 holds number of transfers transfer counter number of transfers number of transfers fixed decremented every transfer. loaded with etcrh value when count reaches h'00 legend mar : memory address register ioar : i/o address register etcr : transfer count register dtdir : data transfer direction bit 205 mar specifies the start address of the transfer source or transfer destination as 24 bits. mar is incremented or decremented by 1 or 2 each time a byte or word is transferred. ioar specifies the lower 16 bits of the other address. the 8 bits above ioar have a value of h'ff. the number of transfers is specified as 8 bits by etcrh and etcrl. the maximum number of transfers, when h'00 is set in both etcrh and etcrl, is 256. in repeat mode, etcrl functions as the transfer counter, and etcrh is used to hold the number of transfers. etcrl is decremented by 1 each time a transfer is executed, and when its value reaches h'00, it is loaded with the value in etcrh. at the same time, the value set in mar is restored in accordance with the values of the dtsz and dtid bits in dmacr. the mar restoration operation is as shown below. mar = mar C (C1) dtid 2 dtsz etcrh the same value should be set in etcrh and etcrl. in repeat mode, operation continues until the dte bit is cleared. to end the transfer operation, therefore, you should clear the dte bit to 0. a transfer end interrupt request is not sent to the cpu or dtc. by setting the dte bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the dte bit was cleared. 206 figure 7-7 illustrates operation in repeat mode. address t address b transfer ioar 1 byte or word transfer performed in response to 1 transfer request legend address t = l address b = l + (C1) dtid ? (2 dtsz ? (nC1)) where : l = value set in mar n = value set in etcr figure 7-7 operation in repeat mode transfer requests (activation sources) consist of external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 2 compare match/input capture a interrupts. external requests can be set for channel b only. 207 figure 7-8 shows an example of the setting procedure for repeat mode. repeat mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl repeat mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. ? clear the fae bit to 0 to select short address mode. ? specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address and transfer destination address in mar and ioar. [3] set the number of transfers in both etcrh and etcrl. [4] set each bit in dmacr. ? set the transfer data size with the dtsz bit. ? specify whether mar is to be incremented or decremented with the dtid bit. ? set the rpe bit to 1. ? specify the transfer direction with the dtdir bit. ? select the activation source with bits dtf3 to dtf0. [5] read the dte bit in dmabcrl as 0. [6] set each bit in dmabcrl. ? clear the dtie bit to 0. ? set the dte bit to 1 to enable transfer. figure 7-8 example of repeat mode setting procedure 208 7.5.5 normal mode in normal mode, transfer is performed with channels a and b used in combination. normal mode can be specified by setting the fae bit in dmabcr to 1 and clearing the blke bit in dmacra to 0. in normal mode, mar is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in etcra. the transfer source is specified by mara, and the transfer destination by marb. table 7-10 summarizes register functions in normal mode. table 7-10 register functions in normal mode register function initial setting operation 23 0 mara source address register start address of transfer source incremented/decremented every transfer, or fixed 23 0 marb destination address register start address of transfer destination incremented/decremented every transfer, or fixed 0 15 etcra transfer counter number of transfers decremented every transfer; transfer ends when count reaches h'0000 legend mara : memory address register a marb : memory address register b etcra : transfer count register a mara and marb specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. mar can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. incrementing, decrementing, or holding a fixed value can be set separately for mara and marb. the number of transfers is specified by etcra as 16 bits. etcra is decremented each time a transfer is performed, and when its value reaches h'0000 the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this time, an interrupt request is sent to the cpu or dtc. the maximum number of transfers, when h'0000 is set in etcra, is 65,536. 209 figure 7-9 illustrates operation in normal mode. address t a address b a transfer address t b legend address address address address where : address b b = l a = l b = l a + saide ? (C1) said ? (2 dtsz ? (nC1)) = l b + daide ? (C1) daid ? (2 dtsz ? (nC1)) = value set in mara = value set in marb = value set in etcra t a t b b a b b l a l b n figure 7-9 operation in normal mode transfer requests (activation sources) are external requests and auto-requests. with auto-request, the dmac is only activated by register setting, and the specified number of transfers are performed automatically. with auto-request, cycle steal mode or burst mode can be selected. in cycle steal mode, the bus is released to another bus master each time a transfer is performed. in burst mode, the bus is held continuously until transfer ends. 210 for setting details, see section 7.3.4, dma controller register (dmacr). figure 7-10 shows an example of the setting procedure for normal mode. normal mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl normal mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. ? set the fae bit to 1 to select full address mode. ? specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address in mara, and the transfer destination address in marb. [3] set the number of transfers in etcra. [4] set each bit in dmacra and dmacrb. ? set the transfer data size with the dtsz bit. ? specify whether mara is to be incremented, decremented, or fixed, with the said and saide bits. ? clear the blke bit to 0 to select normal mode. ? specify whether marb is to be incremented, decremented, or fixed, with the daid and daide bits. ? select the activation source with bits dtf3 to dtf0. [5] read dte = 0 and dtme = 0 in dmabcrl. [6] set each bit in dmabcrl. ? specify enabling or disabling of transfer end interrupts with the dtie bit. ? set both the dtme bit and the dte bit to 1 to enable transfer. figure 7-10 example of normal mode setting procedure 211 7.5.6 block transfer mode in block transfer mode, transfer is performed with channels a and b used in combination. block transfer mode can be specified by setting the fae bit in dmabcr and the blke bit in dmacra to 1. in block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. the transfer source is specified by mara, and the transfer destination by marb. either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). table 7-11 summarizes register functions in block transfer mode. table 7-11 register functions in block transfer mode register function initial setting operation 23 0 mara source address register start address of transfer source incremented/decremented every transfer, or fixed 23 0 marb destination address register start address of transfer destination incremented/decremented every transfer, or fixed 0 etcrah 7 0 etcral 7 holds block size block size counter block size block size fixed decremented every transfer; etcrh value copied when count reaches h'00 15 0 etcrb block transfer counter number of block transfers decremented every block transfer; transfer ends when count reaches h'0000 legend mara : memory address register a marb : memory address register b etcra : transfer count register a etcrb : transfer count register b mara and marb specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. mar can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. incrementing, decrementing, or holding a fixed value can be set separately for mara and marb. 212 whether a block is to be designated for mara or for marb is specified by the blkdir bit in dmacra. to specify the number of transfers, if m is the size of one block (where m = 1 to 256) and n transfers are to be performed (where n = 1 to 65,536), m is set in both etcrah and etcral, and n in etcrb. figure 7-11 illustrates operation in block transfer mode when marb is designated as a block area. address t a address b a transfer address t b address b b 1st block 2nd block nth block block area consecutive transfer of m bytes or words is performed in response to one request legend address address address address where : = l a = l b = l a + saide (C1) said (2 dtsz (mnC1)) = l b + daide (C1) daid (2 dtsz (nC1)) = value set in mara = value set in marb = value set in etcrb = value set in etcrah and etcral t a t b b a b b l a l b n m figure 7-11 operation in block transfer mode (blkdir = 0) 213 figure 7-12 illustrates operation in block transfer mode when mara is designated as a block area. address t b address b b transfer address t a address b a 1st block 2nd block nth block block area consecutive transfer of m bytes or words is performed in response to one request legend address address address address where : = l a = l b = l a + saide (C1) said (2 dtsz (nC1)) = l b + daide (C1) daid (2 dtsz (mnC1)) = value set in mara = value set in marb = value set in etcrb = value set in etcrah and etcral t a t b b a b b l a l b n m figure 7-12 operation in block transfer mode (blkdir = 1) 214 etcral is decremented by 1 each time a byte or word transfer is performed. in response to a single transfer request, burst transfer is performed until the value in etcral reaches h'00. etcral is then loaded with the value in etcrah. at this time, the value in the mar register for which a block designation has been given by the blkdir bit in dmacra is restored in accordance with the dtsz, said/daid, and saide/daide bits in dmacr. etcrb is decremented by 1 every block transfer, and when the count reaches h'0000 the dte bit is cleared and transfer ends. if the dtie bit is set to 1 at this point, an interrupt request is sent to the cpu or dtc. figure 7-13 shows the operation flow in block transfer mode. 215 acquire bus etcral=etcralC1 transfer request? etcral=h'00 release bus blkdir=0 etcral=etcrah etcrb=etcrbC1 etcrb=h'0000 start (dte = dtme = 1) read address specified by mara mara=mara+saide(C1) said 2 dtsz write to address specified by marb marb=marb+daide(C1) daid 2 dtsz marb=marb C daide( C 1) daid 2 dtsz etcrah mara=mara C saide(C1) said 2 dtsz etcrah no yes no yes no yes no yes clear dte bit to 0 to end transfer figure 7-13 operation flow in block transfer mode transfer requests (activation sources) consist of external requests, sci transmission complete and reception complete interrupts, and tpu channel 0 to 2 compare match/input capture a interrupts. for details, see section 7.3.4, dma control register (dmacr). 216 figure 7-14 shows an example of the setting procedure for block transfer mode. block transfer mode setting set dmabcrh set transfer source and transfer destination addresses set number of transfers set dmacr read dmabcrl set dmabcrl block transfer mode [1] [2] [3] [4] [5] [6] [1] set each bit in dmabcrh. ? set the fae bit to 1 to select full address mode. ? specify enabling or disabling of internal interrupt clearing with the dta bit. [2] set the transfer source address in mara, and the transfer destination address in marb. [3] set the block size in both etcrah and etcral. set the number of transfers in etcrb. [4] set each bit in dmacra and dmacrb. ? set the transfer data size with the dtsz bit. ? specify whether mara is to be incremented, decremented, or fixed, with the said and saide bits. ? set the blke bit to 1 to select block transfer mode. ? specify whether the transfer source or the transfer destination is a block area with the blkdir bit. ? specify whether marb is to be incremented, decremented, or fixed, with the daid and daide bits. ? select the activation source with bits dtf3 to dtf0. [5] read dte = 0 and dtme = 0 in dmabcrl. [6] set each bit in dmabcrl. ? specify enabling or disabling of transfer end interrupts to the cpu with the dtie bit. ? set both the dtme bit and the dte bit to 1 to enable transfer. figure 7-14 example of block transfer mode setting procedure 217 7.5.7 dmac activation sources dmac activation sources consist of internal interrupts, external requests, and auto-requests. the activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12. table 7-12 dmac activation sources short address mode full address mode activation source channels 0a and 1a channels 0b and 1b normal mode block transfer mode internal txi0 x interrupts rxi0 x txi1 x rxi1 x tgi0a x tgi1a x tgi2a x external dreq pin falling edge input x requests dreq pin low-level input x auto-request x x x legend : can be specified x : cannot be specified activation by internal interrupt: an interrupt request selected as a dmac activation source can be sent simultaneously to the cpu and dtc. for details, see section 5, interrupt controller. with activation by an internal interrupt, the dmac accepts the request independently of the interrupt controller. consequently, interrupt controller priority settings are not accepted. if the dmac is activated by a cpu interrupt source or an interrupt source that is not used as a dtc activation source (dta = 1), the interrupt source flag is cleared automatically by the dma transfer. with txi and rxi interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a dma transfer. if the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highest-priority channel is activated first. transfer requests for other channels are held pending in the dmac, and activation is carried out in order of priority. 218 when dte = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the dmac, regardless of the dta bit. in this case, the relevant interrupt request is sent to the cpu or dtc. in case of overlap with a cpu interrupt source or dtc activation source (dta = 0), the interrupt request flag is not cleared by the dmac. activation by external request: if an external request ( dreq pin) is specified as an activation source, the relevant port should be set to input mode in advance. level sensing or edge sensing can be used for external requests. external request operation in normal mode (short address mode or full address mode) is described below. when edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the dreq pin. the next transfer may not be performed if the next edge is input before transfer is completed. when level sensing is selected, the dmac stands by for a transfer request while the dreq pin is held high. while the dreq pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. if the dreq pin goes high in the middle of a transfer, the transfer is interrupted and the dmac stands by for a transfer request. activation by auto-request: auto-request activation is performed by register setting only, and transfer continues to the end. with auto-request activation, cycle steal mode or burst mode can be selected. in cycle steal mode, the dmac releases the bus to another bus master each time a byte or word is transferred. dma and cpu cycles usually alternate. in burst mode, the dmac keeps possession of the bus until the end of the transfer, and transfer is performed continuously. 219 7.5.8 basic dmac bus cycles an example of the basic dmac bus cycle timing is shown in figure 7-15. in this example, word- size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. when the bus is transferred from the cpu to the dmac, a source address read and destination address write are performed. the bus is not released in response to another bus request, etc., between these read and write operations. as with cpu cycles, dma cycles conform to the bus controller settings. ? address bus dmac cycle (1-word transfer) rd lwr hwr source address destination address cpu cycle cpu cycle t1 t2 t3 t1 t2 t3 t1 t2 figure 7-15 example of dma transfer bus timing the address is not output to the external address bus in an access to on-chip memory or an internal i/o register. 220 7.5.9 dmac bus cycles (dual address mode) short address mode: figure 7-16 shows a transfer example in which tend output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal i/o space. dma read ? address bus rd lwr tend hwr bus release last transfer cycle dma write dma dead dma read dma write dma read dma write bus release bus release bus release figure 7-16 example of short address mode transfer a one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle. in repeat mode, when tend output is enabled, tend output goes low in the transfer cycle in which the transfer counter reaches 0. 221 full address mode (cycle steal mode): figure 7-17 shows a transfer example in which tend output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. dma read ? address bus rd lwr tend hwr bus release last transfer cycle dma write dma read dma write dma read dma write dma dead bus release bus release bus release figure 7-17 example of full address mode (cycle steal) transfer a one-byte or one-word transfer is performed, and after the transfer the bus is released. while the bus is released one bus cycle is inserted by the cpu or dtc. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle. 222 full address mode (burst mode): figure 7-18 shows a transfer example in which tend output is enabled and word-size full address mode transfer (burst mode) is performed from external 16- bit, 2-state access space to external 16-bit, 2-state access space. dma read ? address bus rd lwr tend hwr bus release dma write dma dead dma read dma write dma read dma write bus release burst transfer last transfer cycle figure 7-18 example of full address mode (burst mode) transfer in burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. in the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state dma dead cycle is inserted after the dma write cycle. if a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. if an nmi is generated while a channel designated for burst transfer is in the transfer enabled state, the dtme bit is cleared and the channel is placed in the transfer disabled state. if burst transfer has already been activated inside the dmac, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. if the last transfer cycle of the burst transfer has already been activated inside the dmac, execution continues to the end of the transfer even if the dtme bit is cleared. 223 full address mode (block transfer mode): figure 7-19 shows a transfer example in which tend output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. dma read ? address bus rd lwr tend hwr bus release block transfer last block transfer dma write dma read dma write dma dead dma read dma write dma read dma write dma dead bus release bus release figure 7-19 example of full address mode (block transfer mode) transfer a one-block transfer is performed for one transfer request, and after the transfer the bus is released. while the bus is released, one or more bus cycles are inserted by the cpu or dtc. in the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one- state dma dead cycle is inserted after the dma write cycle. one block is transmitted without interruption. nmi generation does not affect block transfer operation. 224 dreq pin falling edge activation timing: set the dta bit for the channel for which the dreq pin is selected to 1. figure 7-20 shows an example of dreq pin falling edge activated normal mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of ?, and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. start of dma cycle; dreq pin high level sampling on the rising edge of ? starts. when the dreq pin high level has been sampled, acceptance is resumed after the write cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of ?, and the request is held.) dma read ? address bus dreq idle write idle bus release dma control channel write idle transfer source request minimum of 2 cycles [1] [3] [2] [4] [6] [5] [7] acceptance resumes acceptance resumes dma write bus release dma read dma write bus release request minimum of 2 cycles transfer destination transfer source transfer destination request clear period request clear period read read figure 7-20 example of dreq pin falling edge activated normal mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next ? cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared, and dreq pin high level sampling for edge detection is started. if dreq pin high level sampling has been completed by the time the dma write cycle ends, acceptance resumes after the end of the write cycle, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends. 225 figure 7-21 shows an example of dreq pin falling edge activated block transfer mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of ?, and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. start of dma cycle; dreq pin high level sampling on the rising edge of ? starts. when the dreq pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of ?, and the request is held.) dma read ? address bus dreq idle write bus release dma control channel write transfer source request minimun of 2 cycles [1] [3] [2] [4] [6] [5] [7] acceptance resumes dma dead 1 block transfer idle dead dead dma write bus release dma read dma write dma dead bus release transfer source transfer destination request clear period minimun of 2 cycles request acceptance resumes 1 block transfer request clear period read read transfer destination idle figure 7-21 example of dreq pin falling edge activated block transfer mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next ? cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared, and dreq pin high level sampling for edge detection is started. if dreq pin high level sampling has been completed by the time the dma dead cycle ends, acceptance resumes after the end of the dead cycle, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends. 226 dreq level activation timing (normal mode): set the dta bit for the channel for which the dreq pin is selected to 1. figure 7-22 shows an example of dreq level activated normal mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of ?, and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. the dma cycle is started. acceptance is resumed after the write cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of ?, and the request is held.) dma read dma write ? address bus dreq idle write idle bus release dma control channel write idle transfer source bus release dma read dma write bus release request minimum of 2 cycles [1] [3] [2] minimum of 2 cycles [4] [6] [5] [7] acceptance resumes acceptance resumes transfer destination transfer source transfer destination request read request clear period read request clear period figure 7-22 example of dreq level activated normal mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next ? cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared. after the end of the write cycle, acceptance resumes, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends. 227 figure 7-23 shows an example of dreq level activated block transfer mode transfer. [1] [2] [5] [3] [6] [4] [7] note: in write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. acceptance after transfer enabling; the dreq pin low level is sampled on the rising edge of ?, and the request is held. the request is cleared at the next bus break, and activation is started in the dmac. the dma cycle is started. acceptance is resumed after the dead cycle is completed. (as in [1], the dreq pin low level is sampled on the rising edge of ?, and the request is held.) dma read dma right ? address bus dreq idle write bus release dma control channel write transfer source request [1] [3] [2] [4] [6] [5] [7] acceptance resumes dma dead bus release dma read dma right dma dead bus release 1 block transfer idle dead dead 1 block transfer acceptance resumes request minimum of 2 cycles transfer destination transfer source transfer destination minimum of 2 cycles read request clear period read request clear period idle figure 7-23 example of dreq level activated block transfer mode transfer dreq pin sampling is performed every cycle, with the rising edge of the next ? cycle after the end of the dmabcr write cycle for setting the transfer enabled state as the starting point. when the dreq pin low level is sampled while acceptance by means of the dreq pin is possible, the request is held in the dmac. then, when activation is initiated in the dmac, the request is cleared. after the end of the dead cycle, acceptance resumes, dreq pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.10 dmac multi-channel operation the dmac channel priority order is: channel 0 > channel 1, and channel a > channel b. table 7-13 summarizes the priority order for dmac channels. 228 table 7-13 dmac channel priority order short address mode full address mode priority channel 0a channel 0 high channel 0b channel 1a channel 1 channel 1b low if transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the dmac selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7-13. during burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. figure 7-24 shows a transfer example in which transfer requests are issued simultaneously for channels 0a, 0b, and 1. dma read dma write dma read dma write dma read dma write dma read ? address bus rd hwr lwr dma control channel 0a channel 0b channel 1 idle write idle read write idle read write read request clear request hold request hold request clear request clear bus release channel 0a transfer bus release channel 0b transfer channel 1 transfer bus release request hold read selection non- selection selection figure 7-24 example of multi-channel transfer 229 7.5.11 relation between the dmac, external bus requests, and the dtc there can be no break between a dma cycle read and a dma cycle write. this means that an external bus release cycle, or dtc cycle is not generated between the external read and external write in a dma cycle. in the case of successive read and write cycles, such as in burst transfer or block transfer, an external bus released state may be inserted after a write cycle. since the dtc has a lower priority than the dmac, the dtc does not operate until the dmac releases the bus. when dma cycle reads or writes are accesses to on-chip memory or internal i/o registers, these dma cycles can be executed at the same time as external bus release. however, simultaneous operation may not be possible when a write buffer is used. 230 7.5.12 nmi interrupts and dmac when an nmi interrupt is requested, burst mode transfer in full address mode is interrupted. an nmi interrupt does not affect the operation of the dmac in other modes. in full address mode, transfer is enabled for a channel when both the dte bit and the dtme bit are set to 1. with burst mode setting, the dtme bit is cleared when an nmi interrupt is requested. if the dtme bit is cleared during burst mode transfer, the dmac discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the cpu. the channel on which transfer was interrupted can be restarted by setting the dtme bit to 1 again. figure 7-25 shows the procedure for continuing transfer when it has been interrupted by an nmi interrupt on a channel designated for burst mode transfer. resumption of transfer on interrupted channel set dtme bit to 1 transfer continues [1] [2] dte= 1 dtme= 0 transfer ends no yes [1] [2] check that dte = 1 and dtme = 0 in dmabcrl write 1 to the dtme bit. figure 7-25 example of procedure for continuing transfer on channel interrupted by nmi interrupt 231 7.5.13 forced termination of dmac operation if the dte bit for the channel currently operating is cleared to 0, the dmac stops on completion of the 1-byte or 1-word transfer in progress. dmac operation resumes when the dte bit is set to 1 again. in full address mode, the same applies to the dtme bit. figure 7-26 shows the procedure for forcibly terminating dmac operation by software. forced termination of dmac clear dte bit to 0 forced termination [1] [1] clear the dte bit in dmabcrl to 0. if you want to prevent interrupt generation after forced termination of dmac operation, clear the dtie bit to 0 at the same time. figure 7-26 example of procedure for forcibly terminating dmac operation 232 7.5.14 clearing full address mode figure 7-27 shows the procedure for releasing and initializing a channel designated for full address mode. after full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. clearing full address mode stop the channel initialize dmacr clear fae bit to 0 initialization; operation halted [1] [2] [3] [1] clear both the dte bit and the dtme bit in dmabcrl to 0; or wait until the transfer ends and the dte bit is cleared to 0, then clear the dtme bit to 0. also clear the corresponding dtie bit to 0 at the same time. [2] clear all bits in dmacra and dmacrb to 0. [3] clear the fae bit in dmabcrh to 0. figure 7-27 example of procedure for clearing full address mode 233 7.6 interrupts the sources of interrupts generated by the dmac are transfer end and transfer break. table 7-14 shows the interrupt sources and their priority order. table 7-14 interrupt source priority order interrupt interrupt source interrupt name short address mode full address mode priority order dend0a interrupt due to end of transfer on channel 0a interrupt due to end of transfer on channel 0 high dend0b interrupt due to end of transfer on channel 0b interrupt due to break in transfer on channel 0 dend1a interrupt due to end of transfer on channel 1a interrupt due to end of transfer on channel 1 dend1b interrupt due to end of transfer on channel 1b interrupt due to break in transfer on channel 1 low enabling or disabling of each interrupt source is set by means of the dtie bit for the corresponding channel in dmabcr, and interrupts from each source are sent to the interrupt controller independently. the relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7-14. figure 7-28 shows a block diagram of a transfer end/transfer break interrupt. an interrupt is always generated when the dtie bit is set to 1 while dte bit is cleared to 0. dte/ dtme dtie transfer end/transfer break interrupt figure 7-28 block diagram of transfer end/transfer break interrupt in full address mode, a transfer break interrupt is generated when the dtme bit is cleared to o while dtieb bit is set to 1. in both short address mode and full address mode, dmabcr should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. 234 7.7 usage notes dmac register access during operation: except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. the operating channel setting should only be changed when transfer is disabled. also, the dmac register should not be written to in a dma transfer. dmac register reads during operation (including the transfer waiting state) are described below. (a) dmac control starts one cycle before the bus cycle, with output of the internal address. consequently, mar is updated in the bus cycle before dmac transfer. figure 7-29 shows an example of the update timing for dmac registers in dual address transfer mode. [1] transfer source address register mar operation (incremented/decremented/fixed) transfer counter etcr operation (decremented) block size counter etcr operation (decremented in block transfer mode) [2] transfer destination address register mar operation (incremented/decremented/fixed) [2'] transfer destination address register mar operation (incremented/decremented/fixed) block transfer counter etcr operation (decremented, in last transfer cycle of a block in block transfer mode) [3] transfer address register mar restore operation (in block or repeat transfer mode) transfer counter etcr restore (in repeat transfer mode block size counter etcr restore (in block transfer mode) notes: 1. in single address transfer mode, the update timing is the same as [1]. 2. the mar operation is post-incrementing/decrementing of the dma internal address value. [3] [2'] [2] [1] [1] dma transfer cycle dma read dma read dma write dma write dma dead dma internal address dma control dma register operation dma last transfer cycle transfer destination transfer destination transfer source transfer source idle idle idle read read dead write write ? figure 7-29 dmac register update timing 235 (b) if a dmac transfer cycle occurs immediately after a dmac register read cycle, the dmac register is read as shown in figure 7-30. [2] [1] note: the lower word of mar is the updated value after the operation in [1]. cpu longword read dma transfer cycle mar upper word read mar lower word read dma read dma write dma internal address dma control dma register operation transfe source transfer destination idle ? read write idle figure 7-30 contention between dmac register update and cpu read module stop: when the mstpa7 bit in mstpcr is set to 1, the dmac clock stops, and the module stop state is entered. however, 1 cannot be written to the mstpa7 bit if any of the dmac channels is enabled. this setting should therefore be made when dmac operation is stopped. when the dmac clock stops, dmac register accesses can no longer be made. since the following dmac register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. ? transfer end/suspend interrupt (dte = 0 and dtie = 1) ? tend pin enable (tee = 1) medium-speed mode: when the dta bit is 0, internal interrupt signals specified as dmac transfer sources are edge-detected. in medium-speed mode, the dmac operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. consequently, if the period in which the relevant interrupt source is cleared by the cpu, dtc, or another dmac channel, and the next interrupt is generated, is less than one state with respect to the dmac clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. also, in medium-speed mode, dreq pin sampling is performed on the rising edge of the medium- speed clock. 236 activation by falling edge on dreq pin: dreq pin falling edge detection is performed in synchronization with dmac internal operations. the operation is as follows: [1] activation request wait state: waits for detection of a low level on the dreq pin, and switches to [2]. [2] transfer wait state: waits for dmac data transfer to become possible, and switches to [3]. [3] activation request disabled state: waits for detection of a high level on the dreq pin, and switches to [1]. after dmac transfer is enabled, a transition is made to [1]. thus, initial activation after transfer is enabled is performed by detection of a low level. activation source acceptance: at the start of activation source acceptance, a low level is detected in both dreq pin falling edge sensing and low level sensing. similarly, in the case of an internal interrupt, the interrupt request is detected. therefore, a request is accepted from an internal interrupt or dreq pin low level that occurs before execution of the dmabcrl write to enable transfer. when the dmac is activated, take any necessary steps to prevent an internal interrupt or dreq pin low level remaining from the end of the previous transfer, etc. internal interrupt after end of transfer: when the dte bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the cpu or dtc even if dta is set to 1. also, if internal dmac activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if dta is set to 1. an internal interrupt request following the end of transfer or an abort should be handled by the cpu as necessary. channel re-setting: to reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform dmabcr control bit operations exclusively. note, in particular, that in cases where multiple interrupts are generated between reading and writing of dmabcr, and a dmabcr operation is performed during new interrupt handling, the dmabcr write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. ensure that overlapping dmabcr operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. also, when the dte and dtme bits are cleared by the dmac or are written with 0, they must first be read while cleared to 0 before the cpu can write a 1 to them. 237 section 8 data transfer controller (dtc) 8.1 overview the h8s/2214 includes a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 8.1.1 features the features of the dtc are: ? transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) ? wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected ? direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after the specified data transfers have completely ended ? activation by software is possible ? module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode. 238 8.1.2 block diagram figure 8-1 shows a block diagram of the dtc. the dtcs register information is stored in the on-chip ram*. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc service request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend mra, mrb cra, crb sar dar dtcera to dtcerf, dtceri dtvecr dtcera to dtcerf, dtceri dtvecr : dtc mode registers a and b : dtc transfer count registers a and b : dtc source address register : dtc destination address register : dtc enable registers a to f and i : dtc vector register figure 8-1 block diagram of dtc 239 8.1.3 register configuration table 8-1 summarizes the dtc registers. table 8-1 dtc registers name abbreviation r/w initial value address* 1 dtc mode register a mra * 2 undefined * 3 dtc mode register bmrb* 2 undefined * 3 dtc source address register sar * 2 undefined * 3 dtc destination address register dar * 2 undefined * 3 dtc transfer count register a cra * 2 undefined * 3 dtc transfer count register bcrb * 2 undefined * 3 dtc enable registers dtcer r/w h'00 h'ff16 to h'fe1b, h'fe1e dtc vector register dtvecr r/w h'00 h'fe1f module stop control register a mstpcra r/w h'3f h'fde8 notes: *1 lower 16 bits of the address. *2 registers within the dtc cannot be read or written to directly. *3 register information is located in on-chip ram addresses h'ebc0 to h'efbf. it cannot be located in external memory space. when the dtc is used, do not clear the rame bit in syscr to 0. 240 8.2 register descriptions 8.2.1 dtc mode register a (mra) 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mra is an 8-bit register that controls the dtc operating mode. bits 7 and 6source address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0description 0 sar is fixed 1 0 sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 sar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) bits 5 and 4destination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0description 0 dar is fixed 1 0 dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 dar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) 241 bits 3 and 2dtc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1 bit 1dtc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0dtc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer 242 8.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 4 3 0 2 1 bit initial value : : r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mrb is an 8-bit register that controls the dtc operating mode. bit 7dtc chain transfer enable (chne): specifies chain transfer. with chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer is not performed. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6dtc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0reserved: these bits have no effect on dtc operation in the h8s/2214, and should always be written with 0. 243 8.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 8.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 8.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated. 244 8.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 8.2.7 dtc enable registers (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : the dtc enable registers comprise seven 8-bit readable/writable registers, dtcera to dtcerf and dtceri, with bits corresponding to the interrupt sources that can control enabling and disabling of dtc activation. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable registers are initialized to h'00 by a reset and in hardware standby mode. bit ndtc activation enable (dtcen) bit n dtcen description 0 dtc activation by this interrupt is disabled (initial value) [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended 1 dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 8-4, together with the vector number generated for each interrupt controller. 245 for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 notes: *1 only 1 can be written to the swdte bit. *2 bits dtvec6 to dtvec0 can be written to when swdte = 0. bit initial value r/w : : : dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode. bit 7dtc software activation enable (swdte): enables or disables dtc activation by software. bit 7 swdte description 0 dtc software activation is disabled (initial value) [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 is written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu 1 dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation bits 6 to 0dtc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420. 246 8.2.9 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit : initial value : r/w : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa6 bit in mstpcra is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. for details, see section 17.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 6module stop (mstpa6): specifies the dtc module stop mode. bit 6 mstpa6 description 0 dtc module stop mode cleared (initial value) 1 dtc module stop mode set 247 8.3 operation 8.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 8-2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear an activation flag chne=1 end no no yes yes transfer counter= 0 or disel= 1 clear dtcer interrupt exception handling figure 8-2 flowchart of dtc operation 248 the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 8-2 outlines the functions of the dtc. table 8-2 dtc functions address registers transfer mode activation source transfer source transfer destination ? normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible ? repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues ? block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination ? irq ? tpu tgi ? 8-bit timer cmi ? sci txi or rxi ? a/d converter adi ? software 24 bits 24 bits 249 8.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. an interrupt becomes a dtc activation source when the corresponding bit is set to 1, and a cpu interrupt source when the bit is cleared to 0. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding dtcer bit is cleared. table 8-3 shows activation source and dtcer clearance. the activation source flag, in the case of rxi0, for example, is the rdrf flag of sci0. table 8-3 activation source and dtcer clearance activation source when the disel bit is 0 and the specified number of transfers have not ended when the disel bit is 1, or when the specified number of transfers have ended software activation the swdte bit is cleared to 0 the swdte bit remains set to 1 an interrupt is issued to the cpu interrupt activation the corresponding dtcer bit remains set to 1 the activation source flag is cleared to 0 the corresponding dtcer bit is cleared to 0 the activation source flag remains set to 1 a request is issued to the cpu for the activation source interrupt figure 8-3 shows a block diagram of activation source control. for details see section 5, interrupt controller. on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear controller select interrupt request source flag cleared clear clear request interrupt mask figure 8-3 block diagram of dtc activation source control 250 when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. 8.3.3 dtc vector table figure 8-4 shows the correspondence between dtc vector addresses and register information. table 8-4 shows the correspondence between activation and vector addresses. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] << 1) (where << 1 indicates a 1-bit left shift). for example, if dtvecr is h'10, the vector address is h'0420. the dtc reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. the register information can be placed at predetermined addresses in the on-chip ram. the start address of the register information should be an integral multiple of four. the configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. these two bytes specify the lower bits of the address in the on-chip ram. note: * not available in the h8s/2214. 251 table 8-4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0] <<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 tgi0a (gr0a compare match/ input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/ input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/ input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/ input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare match/ input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/ input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/ input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/ input capture) 45 h'045a dtcec6 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0. 252 interrupt source origin of interrupt source vector number vector address dtce priority dend0a (channel 0/channel 0a transfer end) dmac 72 h'0490 dtcee7 high dend0b (channel 0b transfer end) 73 h'0492 dtcee6 dend1a (channel 1/channel 1a transfer end) 74 h'0494 dtcee5 dend1b (channel 1b transfer end) 75 h'0496 dtcee4 rxi0 (reception complete 0) sci 81 h'04a2 dtcee3 txi0 (transmit data empty 0) channel 0 82 h'04a4 dtcee2 rxi1 (reception complete 1) sci 85 h'04aa dtcee1 txi1 (transmit data empty 1) channel 1 86 h'04ac dtcee0 rxi2 (reception complete 2) sci 89 h'04b2 dtcef7 txi2 (transmit data empty 2) channel 2 90 h'04b4 dtcef6 exirq0 external module 104 h'04d0 dtceg7 exirq1 105 h'04d2 dtceg6 exirq2 106 h'04d4 dtceg5 exirq3 107 h'04d6 dtceg4 exirq4 108 h'04d8 dtceg3 exirq5 109 h'04da dtceg2 exirq6 110 h'04dc dtceg1 exirq7 111 h'04de dtceg0 low register information start address register information chain transfer dtc vector address figure 8-4 correspondence between dtc vector address and register information 253 8.3.4 location of register information in address space figure 8-5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (contents of the vector address). in the case of chain transfer, register information should be located in consecutive areas. locate the register information in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information start address chain transfer register information chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0 123 sar mrb dar figure 8-5 location of register information in address space 8.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. 254 table 8-5 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register bcrb not used transfer sar dar figure 8-6 memory mapping in normal mode 8.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. 255 table 8-6 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register bcrb not used transfer sar or dar dar or sar repeat area figure 8-7 memory mapping in repeat mode 8.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. 256 table 8-7 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register bcrb transfer count transfer sar or dar dar or sar block area first block nth block figure 8-8 memory mapping in block transfer mode 257 8.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 8-9 shows the memory map for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 8-9 chain transfer memory map in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected. 258 8.3.9 operation timing figures 8-10 to 8-12 show an example of dtc operation timing. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write ? figure 8-10 dtc operation timing (example in normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read ? dtc activation request dtc request address figure 8-11 dtc operation timing (example of block transfer mode, with block size of 2) 259 read write read write address ? dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 8-12 dtc operation timing (example of chain transfer) 8.3.10 number of dtc execution states table 8-8 lists execution statuses for a single dtc data transfer, and table 8-9 shows the number of states required for each execution status. table 8-8 dtc execution statuses mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral) 260 table 8-9 number of states required for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 16 access states 112223 23 vector read s i 1 4 6 + 2 m 2 3 + m execution status register s j information read/write byte data read s k word data read s k byte data write s l word data write s l 1 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 2 4 2 4 3 + m 6 + 2 m 3 + m 6 + 2 m 2 2 2 2 3 + m 3 + m 3 + m 3 + m internal operation s m 1 m: number of wait states in external device access the number of execution states is calculated from the formula below. note that means the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i s i + (j s j + k s k + l s l ) + m s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states. 261 8.3.11 procedures for using dtc activation by interrupt: the procedure for using the dtc with interrupt activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. [5] after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. activation by software: the procedure for using the dtc with software activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] check that the swdte bit is 0. [4] write 1 to swdte bit and the vector number to dtvecr. [5] check the vector number written to dtvecr. [6] after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested. 262 8.3.12 examples of use of the dtc (1) normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. [1] set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. [2] set the start address of the register information at the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. [5] each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. [6] when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing. 263 (2) software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. [1] set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. [2] set the start address of the register information at the dtc vector address (h'04c0). [3] check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. [4] write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. [5] read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. [6] if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. [7] after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing. 264 8.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 8.5 usage notes module stop: when the mstpa6 bit in mstpcra is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. on-chip ram: the mra, mrb, sar, dar, cra, and crb registers are all located in on-chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. dmac transfer end interrupt: when dtc transfer is activated by a dmac transfer end interrupt, the dmac's dte bit is not subject to dtc control, regardless of the transfer counter and disel bit, and the write data has priority. consequently, an interrupt request is not sent to the cpu when the dtc transfer counter reaches 0. dtce bit setting: for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 265 section 9 i/o ports 9.1 overview the h8s/2214 has ten i/o ports (ports 1, 3, 7, and a to g), and two input-only ports (ports 4 and 9). table 9-1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only ports), a data register (dr) that stores output data, and a port register (port) used to read the pin states. ports a to e have a built-in mos input pull-up function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off status of the mos input pull-ups. ports 3 and a include an open-drain control register (odr) that controls the on/off status of the output buffer pmos. all the ports can drive a single ttl load and 30 pf capacitive load. the irq pins and external expansion interrupt input pins are schmitt-triggered inputs. block diagrams of each port are shown in appendix c, i/o port block diagrams. 266 table 9-1 h8s/2214 port functions port description pins modes 4 and 5 mode 6 mode 7 port 1 ? 8-bit i/o port ? schmitt- triggered input ( irq1 , irq0 ) p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), and external interrupt input ( irq0 , irq1 ) p13/tiocd0/tclkb/ a23 p12/tiocc0/tclka/ a22 p11/tiocb0/a21 p10/tioca0/a20 8-bit i/o port also functioning as dmac output pins ( dack0 , dack1 ), tpu i/o pins (tclka, tclkb, tioca0, tiocb0, tiocc0, tiocd0), and address output (a20 to a23) port 3 ? 7-bit i/o port ? open-drain output capability ? schmitt- triggered input ( irq5 , irq4 , exirq7 ) p36/ exirq7 p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 7-bit i/o port also functioning as sci (channel 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input ( irq4 , irq5 ), and external extended interrupt input ( exirq7 ) port 4 ? 8-bit input port ? schmitt- triggered input ( exirq6 , to exirq0 ) p47/ exirq6 p46/ exirq5 p45 p44/ exirq4 p43/ exirq3 p42/ exirq2 p41/ exirq1 p40/ exirq0 8-bit input port also functioning as external extended interrupt input pins ( exirq6 to exirq0 ) 267 port description pins modes 4 and 5 mode 6 mode 7 port 7 ? 8-bit i/o port p77 p76/exmstp p75/ exms p74/ mres / exdtce p73/ tend1 / cs7 p72/ tend0 / cs6 p71/ dreq1 / cs5 p70/ dreq0 / cs4 8-bit i/o port also functioning as dmac i/o pins ( dreq0 , tend0 , dreq1 , tend1 ), bus control output pins ( cs4 to cs7 ), the manual reset input pin ( mres ), and external module output pins (exmstp, exms , exdtce ) 8-bit i/o port also functioning as dmac i/o pins ( dreq0 , tend0 , dreq1 , tend1 ), the manual reset input pins ( mres ), and external module output pin (exmstp, exms , exdtce ) port 9 ? 1-bit input port p96/da0 1-bit input port also functioning as d/a analog output pin (d/a0) port a ? 4-bit i/o port ? built-in mos input pull-up ? open-drain output capability pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) and address output (a16 to a19) i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) port b ? 8-bit i/o port ? built-in mos input pull-up pb7/a15 pb6/a14 pb5/a13 pb4/a12 pb3/a11 pb2/a10 pb1/a9 pb0/a8 i/o port also functioning as address output (a8 to a15) i/o port port c ? 8-bit i/o port ? built-in mos input pull-up pc7/a7Cpc0/a0 address output (a0 to a7) when ddr = 0: input port when ddr = 1: address output i/o port port d ? 8-bit i/o port ? built-in mos input pull-up pd7/d15Cpd0/d8 data bus input/output i/o port port e ? 8-bit i/o port ? built-in mos input pull-up pe7/d7Cpe0/d0 8-bit bus mode: i/o port 16-bit bus mode: data bus input/output i/o port 268 port description pins modes 4 and 5 mode 6 mode 7 port f ? 8-bit i/o port ? schmitt- triggered input ( irq3 , irq2 ) pf7/? when ddr = 0: input port when ddr = 1 (after reset): ? output when ddr = 0 (after reset): input port when ddr = 1: ? output pf6/ as pf5/ rd pf4/ hwr as , rd , hwr output i/o port pf3/ lwr / irq3 16-bit bus mode: lwr output 8-bit bus mode: i/o port also functioning as interrupt input pin ( irq3 ) i/o port also functioning as interrupt input pin ( irq3 ) pf2/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port pf1/ back when brle = 0 (after reset): i/o port when brle = 1: back output i/o port pf0/ breq / irq2 when brle = 0 (after reset): i/o port also functioning as interrupt input pin ( irq2 ) when brle = 1: breq input also functioning as interrupt input pin ( irq2 ) i/o port also functioning as interrupt input pin ( irq2 ) port g ? 5-bit i/o port ? schmitt- triggered pg4/ cs0 when ddr = 0* 1 : input port when ddr = 1* 2 : cs0 output i/o port also functioning as interrupt input pins input ( irq7 , irq6 ) pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 when ddr = 0 (after reset): input port also functioning as interrupt input pin ( irq7 ) when ddr = 1: interrupt input pin ( irq7 ) also functions as cs1 , cs2 , cs3 output ( irq6 , irq7 ) pg0/ irq6 notes: *1 after a mode 6 reset *2 after a mode 4 or 5 reset 269 9.2 port 1 9.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt pins ( irq0 and irq1 ), and address bus output pins (a23 to a20). port 1 pin functions depend on the operating mode. the interrupt input pins ( irq0 and irq1 ) are schmitt-triggered inputs. figure 9-1 shows the port 1 pin configuration. p17 p16 p15 p14 p13 p12 p11 p10 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /tiocb2 /tioca2 /tiocb1 /tioca1 /tiocd0 /tiocc0 /tiocb0 /tioca0 /tclkd (input) /tclkc (input) /tclkb (input)/ /tclka (input)/ port 1 pins: pin functions in modes 4 to 6 /irq1 (input) /irq0 (input) a23 (output) a22 (output) /a21 (output) /a20 (output) p17 p16 p15 p14 p13 p12 p11 p10 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /tiocb2 /tioca2 /tiocb1 /tioca1 /tiocd0 /tiocc0 /tiocb0 /tioca0 /tclkd /tclkc (input) /tclkb (input) /tclka (input) (input) pin functions in mode 7 /irq1 (input) /irq0 (input) port 1 figure 9-1 port 1 pin functions 270 9.2.2 register configuration table 9-2 shows the port 1 register configuration. table 9-2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'fe30 port 1 data register p1dr r/w h'00 h'ff00 port 1 register port1 r undefined h'ffb0 note: * lower 16 bits of the address. (1) port 1 data direction register (p1ddr) 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr , w 2 p12ddr 0 w 1 p11ddr 0 w bit : initial value : r/w : p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. p1ddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the tpu is initialized by a manual reset, the pin states in this case are determined by the p1ddr and p1dr specifications. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a)modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, pins p13 to p10 are address outputs. pins p17 to p14, and pins p13 to p10 when address output is disabled, are output ports when the corresponding p1ddr bits are set to 1, and input ports when the corresponding p1ddr bits are cleared to 0. (b)mode 7 setting a p1ddr bit to 1 makes the corresponding port 1 pin an output port, while clearing the bit to 0 makes the pin an input port. 271 (2) port 1 data register (p1dr) 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit : initial value : r/w : p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). p1dr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port 1 register (port1) 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r bit : initial value : r/w : note: * determined by the state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its previous state after a manual reset and in software standby mode. 272 9.2.3 pin functions port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt input pins ( irq0 and irq1 ), and address output pins (a23 to a20). port 1 pin functions are shown in table 9-3. table 9-3 port 1 pin functions pin pin functions and selection method p17/ tiocb2/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 settings (bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, and bits cclr1 and cclr0 in tcr2), bits tpsc2 to tpsc0 in tcr0 and tcr5, and bit p17ddr. tpu channel 2 settings (1) in table below (2) in table below p17ddr 0 1 pin function tiocb2 output p17 input p17 output tiocb2 input* 1 tclkd input* 2 notes: *1 tiocb2 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. *2 tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. also, tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care 273 pin pin functions and selection method p16/ tioca2/ irq1 the pin function is switched as shown below according to the combination of the tpu channel 2 settings (bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, and bits cclr1 and cclr0 in tcr2) and bit p16ddr. tpu channel 2 settings (1) in table below (2) in table below p16ddr 0 1 pin function tioca2 output p16 input p16 output tioca2 input* 1 irq1 input* 2 tpu channel 2 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output* 3 pwm mode 2 output x: dont care notes: *1 tioca2 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. *2 when used as an external interrupt pin, do not use for another function. *3 output is disabled for tiocb2. 274 pin pin functions and selection method p15/ tiocb1/ tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 settings (bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, and bits cclr1 and cclr0 in tcr1), bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, and bit p15ddr. tpu channel 1 settings (1) in table below (2) in table below p15ddr 0 1 pin function tiocb1 output p15 input p15 output tiocb1 input* 1 tclkc input* 2 notes: *1 tiocb1 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. *2 tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110, or the setting for either tcr4 or tcr5 is: tpsc2 to tpsc0 = b'101. also, tclkc input when channels 2 and 4 are set to phase counting mode. tpu channel 1 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: dont care 275 pin pin functions and selection method p14/ tioca1/ irq0 the pin function is switched as shown below according to the combination of the tpu channel 1 settings (bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, and bits cclr1 and cclr0 in tcr1) and bit p14ddr. tpu channel 1 settings (1) in table below (2) in table below p14ddr 0 1 pin function tioca1 output p14 input p14 output tioca1 input* 1 irq0 input* 2 tpu channel 1 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output* 3 pwm mode 2 output x: dont care notes: *1 tioca1 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0= b'10xx. *2 when used as an external interrupt pin, do not use for another function *3 output is disabled for tiocb1. 276 pin pin functions and selection method p13/ tiocd0/ tclkb/ a23 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bits ae3 to ae0 in pfcr, and bit p13ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than b'1111 b'1111 tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p13ddr 0 1 0 1 pin function tiocd0 output p13 input p13 output tiocd0 output p13 input p13 output tiocd0 input* 1 tiocd0 input* 1 tclkb input* 2 a23 output tclkb input* 2 notes: *1 tiocd0 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. *2 tclkb input when the setting for any of tcr0 to tcr2 is: tpsc2 to tpsc0 = b'101. also, tclkb input when channels 1 and 5 are set to phase counting mode. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: dont care 277 pin pin functions and selection method p12/ tiocc0/ tclka/ a22 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bits ae3 to ae0 in pfcr, and bit p12ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than b'1111 b'1111 tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p12ddr 0 1 0 1 pin function tiocc0 output p12 input p12 output tiocc0 output p12 input p12 output tiocc0 input* 1 tiocc0 input* 1 tclka input* 2 a22 output tclka input* 2 tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output* 3 pwm mode 2 output x: dont care notes: *1 tiocc0 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. *2 tclka input when the setting for any of tcr0 to tcr5 is: tpsc2 to tpsc0 = b'100. also, tclka input when channels 1 and 5 are set to phase counting mode. *3 output is disabled for tiocd0. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and the settings in (2) apply. 278 pin pin functions and selection method p11/ tiocb0/ a21 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0 and bits iob3 to iob0 in tior0h), bits ae3 to ae0 in pfcr, and bit p11ddr. operating mode modes 4, 5, 6 ae3 to ae0 b'0000 to b'1101 b'1110 to b'1111 tpu channel0 settings (1) in table below (2) in table below p11ddr 0 1 pin function tiocb0 output p11 input p11 output a21 output tiocb0 input* 1 operating mode mode 7 ae3 to ae0 tpu channel0 settings (1) in table below (2) in table below p11ddr 0 1 pin function tiocb0 output p11 input p11 output tiocb0 input* 1 note: *1 tiocb0 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: dont care 279 pin pin functions and selection method p10/ tioca0/ a20 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bits ae3 to ae0 in pfcr, and bit p10ddr. operating mode modes 4, 5, 6 ae3 to ae0 b'0000 to b'1100 b'1101 to b'1111 tpu channel0 settings (1) in table below (2) in table below p10ddr 0 1 pin function tioca0 output p10 input p10 output a20 output tioca0 input* 1 operating mode mode 7 ae3 to ae0 tpu channel0 settings (1) in table below (2) in table below p10ddr 0 1 pin function tioca0 output p10 input p10 output tioca0 input* 1 tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output* 2 pwm mode 2 output x: dont care notes: *1 tioca0 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. *2 output is disabled for tiocb0. 280 9.3 port 3 9.3.1 overview port 3 is a 7-bit i/o port. port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1), external interrupt input pins ( irq4 and irq5 ), and an external expansion interrupt input pin ( exirq7 ). port 3 pin functions are the same in all operating modes. the interrupt input pins ( irq4 and i rq5 ) and the external expansion interrupt input pin ( exirq7 ) are schmitt-triggered inputs. figure 9-2 shows the port 3 pin configuration. p36 p35 p34 p33 p32 p31 p30 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) / exirq7 (input) /sck1(input/output)/ irq5 (input) /rxd1 (input) /txd1 (output) /sck0(input/output)/ irq4 (input) /rxd0 (input) /txd0 (output) port 3 pins port 3 figure 9-2 port 3 pin functions 9.3.2 register configuration table 9-4 shows the port 3 register configuration. table 9-4 port 3 registers name abbreviation r/w initial value* 2 address* 1 port 3 data direction register p3ddr w h'00 h'fe32 port 3 data register p3dr r/w h'00 h'ff02 port 3 register port3 r h'00 h'ffb2 port 3 open-drain control register p3odr r/w h'00 h'fe46 interrupt request input pin select register 0 ipintsel0 r/w h'00 h'fe4a notes: *1 lower 16 bits of the address. *2 value of bits 6 to 0. 281 (1) port 3 data direction register (p3ddr) 7 undefined 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr , w 2 p32ddr 0 w 1 p31ddr 0 w bit : initial value : r/w : p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be returned. bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p3ddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the sci is initialized by a manual reset, the pin states in this case are determined by the p3ddr and p3dr specifications. (2) port 3 data register (p3dr) 7 undefined 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit : initial value : r/w : p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p36 to p30). bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. p3dr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port 3 register (port3) 7 undefined 6 p36 * r 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r bit : initial value : r/w : note: * determined by the state of pins p36 to p30. 282 port3 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 3 pins (p36 to p30) must always be performed on p3dr. bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port3 contents are determined by the pin states, as p3ddr and p3dr are initialized. port3 retains its previous state after a manual reset and in software standby mode. (4) port 3 open-drain control register (p3odr) 7 undefined 6 p36odr 0 r/w 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit : initial value : r/w : p3odr is an 8-bit readable/writable register that controls the pmos on/off status for each port 3 pin (p36 to p30). bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. setting a p3odr bit to 1 makes the corresponding port 3 pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. p3odr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (5) interrupt request input pin select register 0 (ipinsel0) bit:7 65 43 21 0 p36 irq7e p47 irq6e p46 irq5e p44 irq4e p43 irq3e p42 irq2e p41 irq1e p40 irq0e initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w ipinsel0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt request input signals ( exirq0 to exirq7 ) from externally connected modules. ipinsel0 is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state in a manual reset and in software standby mode. 283 bit 7enable of exirq7 input from p36 (p36irq7e): selects whether or not p36 is used as the exirq7 input pin. bit 7 p36irq7e description 0 p36 is not used as exirq7 input (initial value) 1 p36 is used as exirq7 input bit 6enable of exirq6 input from p47 (p47irq6e): selects whether or not p47 is used as the exirq6 input pin. bit 6 p47irq6e description 0 p47 is not used as exirq6 input (initial value) 1 p47 is used as exirq6 input bit 5 enable of exirq5 input from p46 (p46irq5e): selects whether or not p46 is used as the exirq5 input pin. bit 5 p46irq5e description 0 p46 is not used as exirq5 input (initial value) 1 p46 is used as exirq5 input bit 4enable of exirq4 input from p44 (p44irq4e): selects whether or not p44 is used as the exirq4 input pin. bit 4 p44irq4e description 0 p44 is not used as exirq4 input (initial value) 1 p44 is used as exirq4 input 284 bit 3enable of exirq3 input from p43 (p43irq3e): selects whether or not p43 is used as the exirq3 input pin. bit 3 p43irq3e description 0 p43 is not used as exirq3 input (initial value) 1 p43 is used as exirq3 input bit 2enable of exirq2 input from p42 (p42irq2e): selects whether or not p42 is used as the exirq2 input pin. bit 2 p42irq2e description 0 p42 is not used as exirq2 input (initial value) 1 p42 is used as exirq2 input bit 1enable of exirq1 input from p41 (p41irq1e): selects whether or not p41 is used as the exirq1 input pin. bit 1 p41irq1e description 0 p41 is not used as exirq1 input (initial value) 1 p41 is used as exirq1 input bit 0enable of exirq0 input from p40 (p40irq0e): selects whether or not p40 is used as the exirq0 input pin. bit 0 p40irq0e description 0 p40 is not used as exirq0 input (initial value) 1 p40 is used as exirq0 input 285 9.3.3 pin functions port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1), interrupt input pins ( irq4 and irq5 ), and an external expansion interrupt input pin ( exirq7 ). port 3 pin functions are shown in table 9-5. table 9-5 port 3 pin functions pin pin functions and selection method p36 the pin function is switched as shown below according to the combinations of the p36ddr bit and bit p36irq7e in ipinselq. p36irq7e 0 1 p36ddr 0 1 pin function p36 input p36 output * exirq7 input note: * nmos open-drain output when p36odr = 1. p35/sck1/ rq5 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci1, bits cke0 and cke1 in scr, and bit p35ddr. cke1 0 1 c/ a 01 cke0 0 1 p35ddr 0 1 pin function p35 input p35 output* 1 sck1 output* 1 sck1 output* 1 sck1 input irq5 input* 2 notes: *1 nmos open-drain output when p35odr = 1. *2 when used as an external interrupt pin, do not use for another function. p34/rxd1 the pin function is switched as shown below according to the combination of bit re in scr of sci1 and bit p34ddr. re 0 1 p34ddr 0 1 pin function p34 input p34 output * rxd1 input note: * nmos open-drain output when p34odr = 1. 286 pin pin functions and selection method p33/txd1 the pin function is switched as shown below according to the combination of bit te in scr of sci1 and bit p33ddr. te 0 1 p33ddr 0 1 pin function p33 input p33 output * txd1 output * note: * nmos open-drain output when p33odr = 1. p32/sck0/ irq4 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p32ddr. cke1 0 1 c/ a 01 cke0 0 1 p32ddr 0 1 pin function p32 input p32 output* 1 sck0 output* 1 sck0 output* 1 sck0 input irq4 input* 2 notes: *1 nmos open-drain output when p32odr = 1. *2 when used as an external interrupt pin, do not use for another function. p31/rxd0 the pin function is switched as shown below according to the combination of bit re in scr of sci0 and bit p31ddr. re 0 1 p31ddr 0 1 pin function p31 input p31 output * rxd0 input note: * nmos open-drain output when p31odr = 1. p30/txd0 the pin function is switched as shown below according to the combination of bit te in scr of sci0 and bit p30ddr. te 0 1 p30ddr 0 1 pin function p30 input p30 output * txd0 output * note: * nmos open-drain output when p30odr = 1. 287 9.4 port 4 9.4.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as external expansion interrupt input pins ( exirq6 to exirq0 ). port 4 pin functions are the same in all operating modes. figure 9-3 shows the port 4 pin configuration. p47 p46 p45 p44 p43 p42 p41 p40 (input) (input) (input) (input) (input) (input) (input) (input) / exirq6 (input) / exirq5 (input) / exirq4 (input) / exirq3 (input) / exirq2 (input) / exirq1 (input) / exirq0 (input) port 4 pins port 4 figure 9-3 port 4 pin functions 9.4.2 register configuration table 9-6 shows the port 4 register configuration. port 4 is an input-only register, and does not have a data direction register or data register. table 9-6 port 4 registers name abbreviation r/w initial value address * port 4 register port4 r undefined h'ffb3 interrupt request input pin select register 0 ipinsel0 r/w h'00 h'fe4a note: * lower 16 bits of the address. 288 (1) port 4 register (port4) 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r bit : initial value : r/w : note: * determined by the state of pins p47 to p40. port4 is an 8-bit read-only register. the pin states are always read when a port 4 read is performed. this register cannot be written to. (2) interrupt request input pin select register 0 (ipinsel0) bit:7 65 43 21 0 p36 irq7e p47 irq6e p46 irq5e p44 irq4e p43 irq3e p42 irq2e p41 irq1e p40 irq0e initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w ipinsel0 is an 8-bit readable/writable register that selects which pins are to be used for interrupt request input signals ( exirq0 to exirq7 ) from externally connected modules. ipinsel0 is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state in a manual reset and in software standby mode. bit 7enable of exirq7 input from p36 (p36irq7e): selects whether or not p36 is used as the exirq7 input pin. bit 7 p36irq7e description 0 p36 is not used as exirq7 input (initial value) 1 p36 is used as exirq7 input bit 6enable of exirq6 input from p47 (p47irq6e): selects whether or not p47 is used as the exirq6 input pin. bit 6 p47irq6e description 0 p47 is not used as exirq6 input (initial value) 1 p47 is used as exirq6 input 289 bit 5 enable of exirq5 input from p46 (p46irq5e): selects whether or not p46 is used as the exirq5 input pin. bit 5 p46irq5e description 0 p46 is not used as exirq5 input (initial value) 1 p46 is used as exirq5 input bit 4enable of exirq4 input from p44 (p44irq4e): selects whether or not p44 is used as the exirq4 input pin. bit 4 p44irq4e description 0 p44 is not used as exirq4 input (initial value) 1 p44 is used as exirq4 input bit 3enable of exirq3 input from p43 (p43irq3e): selects whether or not p43 is used as the exirq3 input pin. bit 3 p43irq3e description 0 p43 is not used as exirq3 input (initial value) 1 p43 is used as exirq3 input bit 2enable of exirq2 input from p42 (p42irq2e): selects whether or not p42 is used as the exirq2 input pin. bit 2 p42irq2e description 0 p42 is not used as exirq2 input (initial value) 1 p42 is used as exirq2 input 290 bit 1enable of exirq1 input from p41 (p41irq1e): selects whether or not p41 is used as the exirq1 input pin. bit 1 p41irq1e description 0 p41 is not used as exirq1 input (initial value) 1 p41 is used as exirq1 input bit 0enable of exirq0 input from p40 (p40irq0e): selects whether or not p40 is used as the exirq0 input pin. bit 0 p40irq0e description 0 p40 is not used as exirq0 input (initial value) 1 p40 is used as exirq0 input 9.4.3 pin functions port 4 pins also function as external expansion interrupt input pins ( exirq6 to exirq0 ). 291 9.5 port 7 9.5.1 overview port 7 is an 8-bit i/o port. port 7 pins also function as dmac input pins ( dreq0 , tend0 , dreq1 , and tend1 ), bus control output pins ( cs4 to cs7 ), external module output pins (exmstp, exms , and exdtce ), and the manual reset input pin ( mres ). the functions of pins p77 to p74 are the same in all operating mode, but the functions of pins p73 to p70 depend on the operating mode. figure 9-4 shows the port 7 pin configuration. p77 p76 / exmstp p75 / exms p74 / mres / exdtce p73 / tend1 / cs7 p72 / tend0 / cs6 p71 / dreq1 / cs5 p70 / dreq0 / cs4 p77 p76 p75 p74 p73 p72 p71 p70 (input/output) (input/output)/exmstp (output) (input/output)/ exms (output) (input/output)/ mres (input)/ exdtce (output) tend1 (output)/ cs7 (output) (input)/ tend0 (output)/ cs6 (output) (input)/ dreq1 (input)/ cs5 (output) (input)/ dreq0 (input)/ cs4 (output) port 7 pins pin functions in modes 4 to 6 p77 p76 p75 p74 p73 p72 p71 p70 (input/output) (input/output)/exmstp (output) (input/output) (input/output) (input/output)/ tend1 (output) (input/output) (input/output) (input/output)/ dreq0 (input) / exms (output) / mres (input)/ exdtce (output) / tend0 (output) / dreq1 (input) pin functions in mode 7 port 7 figure 9-4 port 7 pin functions 292 9.5.2 register configuration table 9-7 shows the port 7 register configuration. table 9-7 port 7 registers name abbreviation r/w initial value address * port 7 data direction register p7ddr w h'00 h'fe36 port 7 data register p7dr r/w h'00 h'ff06 port 7 register port7 r undefined h'ffb6 external module connection output pin select register opinsel r/w b'-000---- h'fe4e note: * lower 16 bits of the address. (1) port 7 data direction register (p7ddr) 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 0 p70ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w bit : initial value : r/w : p7ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7. p7ddr cannot be read; if it is, an undefined value will be read. setting a p7ddr bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p7ddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the 8-bit timer and sci are initialized by a manual reset, the pin states in this case are determined by the p7ddr and p7dr specifications. (2) port 7 data register (p7dr) 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 0 p70dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w bit : initial value : r/w : p7dr is an 8-bit readable/writable register that stores output data for the port 7 pins (p77 to p70). 293 p7dr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port 7 register (port7) 7 p77 * r 6 p76 * r 5 p75 * r 4 p74 * r 3 p73 * r 0 p70 * r 2 p72 * r 1 p71 * r bit : initial value : r/w : note: * determined by the state of pins p77 to p70. port7 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 7 pins (p77 to p70) must always be performed on p7dr. if a port 7 read is performed while p7ddr bits are set to 1, the p7dr values are read. if a port 7 read is performed while p7ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port7 contents are determined by the pin states, as p7ddr and p7dr are initialized. port7 retains its previous state after a manual reset and in software standby mode. (4) external module connection output pin select register (opinsel) bit:7 65 43 21 0 p76 stpoe p75 msoe p74 dtcoe initial value : undefined 00 0 undefined undefined undefined undefined r/w : r/w r/w r/w opinsel is an 8-bit readable/writable register that selects whether or not output signals ( exdtce , exmstp, exms ) to externally connected modules are output to pins p76 to p74. opinsel bits 6 to 4 are initialized to 000 by a power-on reset and in hardware standby mode. they retain their previous states in a manual reset and in software standby mode. bit 7reserved: this bit will return an undefined value if read, and should only be written with 0. 294 bit 6enable of exmstp output to p76 (p76stpoe): selects whether or not the exmstp module stop signal to external modules (bit 0 in mstpcrb) is output to p76. bit 6 p76stpoe description 0 exmstp is not output to p76 (initial value) 1 exmstp is output to p76 bit 5enable of exms output to p75 (p75msoe): selects whether or not the exms module stop signal to external modules (corresponding to addresses h'ffff40 to h'ffff5f) is output to p75. bit 5 p75msoe description 0 exms is not output to p75 (initial value) 1 exms is output to p75 bit 4enable of exdtce output to p74 (p74dtcoe): selects whether or not the exdtce signal, indicating that dtc transfer corresponding to exirq0 to exirqf input is in progress, is output to p74. this signal is used, for example, when the dtc in the chip has been activated by an interrupt (exirq0 to exirqf) from an external module, and the interrupt request is to be cleared automatically on the external module side by dtc transfer. bit 4 p74dtcoe description 0 exdtce is not output to p74 (initial value) 1 exdtce is output to p74 bits 3 to 0reserved: these bits will return an undefined value if read, and should only be written with 0. 295 9.5.3 pin functions port 7 pins also function as dmac i/o pins ( dreq0 , tend0 , dreq1 , and tend1 ), bus control output pins ( cs4 to cs7 ), external module output pins (exmstp, exms , and exdtce ), and the manual reset input pin ( mres ). port 7 pin functions are shown in table 9-8. table 9-8 port 7 pin functions pin pin functions and selection method p77 the pin function is switched as shown below according to the setting of bit p77ddr. p77ddr 0 1 pin function p77 input p77 output p76/ exmstp the pin function is switched as shown below according to the combination of bit p76stpoe in opinsel and bit p76ddr. p76stpoe 0 1 p76ddr 0 1 pin function p76 input p76 output exmstp output p75/ exms the pin function is switched as shown below according to the combination of bit p75msoe in opinsel and bit p75ddr. p75msoe 0 1 p75ddr 0 1 pin function p75 input p75 output exms output p74/ mres / exdtce the pin function is switched as shown below according to the combination of bit mrese in syscr and bit p74ddr. p74dtcoe 0 1 mrese 0 1 p74ddr 0 1 0 pin function p74 input p74 output mres input exdtce output 296 pin pin functions and selection method p73/ tend1 / cs7 the pin function is switched as shown below according to the combination of the operating mode, bit tee1 in dmatcr of the dmac, and bit p73ddr. operating mode modes 4, 5, 6 mode 7 tee1 0 1 0 1 p73ddr 0 1 0 1 pin function p73 input cs7 output tend1 output p73 input p73 output tend1 output p72/ tend0 / cs6 the pin function is switched as shown below according to the combination of the operating mode, bit tee0 in dmatcr of the dmac, and bit p72ddr. operating mode modes 4, 5, 6 mode 7 tee0 0 1 0 1 p72ddr 0 1 0 1 pin function p72 input cs6 output tend0 output p72 input p72 output tend0 output p71/ dreq1 / cs5 the pin function is switched as shown below according to the combination of the operating mode and bit p71ddr. operating mode modes 4, 5, 6 mode 7 p71ddr 0 1 0 1 pin function p71 input cs5 output p71 input p71 output dreq1 input p70/ dreq0 / cs4 the pin function is switched as shown below according to the combination of the operating mode and bit p70ddr. operating mode modes 4, 5, 6 mode 7 p70ddr 0 1 0 1 pin function p70 input cs4 output p70 input p70 output dreq0 input 297 9.6 port 9 9.6.1 overview port 9 is a 1-bit input-only port. port 9 pins also function as d/a converter analog output pin (da0). port 9 pin functions are the same in all operating modes. figure 9-5 shows the port 9 pin configuration. p96 (input)/da0(output) port 9 pins port 9 figure 9-5 port 9 pin functions 9.6.2 register configuration table 9-9 shows the port 9 register configuration. port 9 is an input-only register, and does not have a data direction register or data register. table 9-9 port 9 registers name abbreviation r/w initial value address * port 9 register port9 r undefined h'ffb8 note: * lower 16 bits of the address. (1) port 9 register (port9) 7 r 6 p96 * r 5 r 4 r 3 r 0 r 2 r 1 r bit : initial value : r/w : note: * determined by the state of pin p96. port9 is an 8-bit read-only register. the pin states are always read when a port 9 read is performed. this register cannot be written to. bits 7 and 5 to 0 are reserved, and will return an undefined value if read. 298 9.6.3 pin functions port 9 pins also function as d/a converter analog output pin (da0). 9.7 port a 9.7.1 overview port a is an 8-bit i/o port. port a pins also function as address bus outputs and sci2 i/o pins (sck2, rxd2, and txd2). the pin functions depend on the operating mode. port a has a built-in mos input pull-up function that can be controlled by software. figure 9-6 shows the port a pin configuration. pa3/a19/sck2 pa2/ a18/rxd2 pa1/ a17/txd2 pa0/ a16 pa3 (input/output) pa2 (input/output) pa1 (input/output) pa0 (input/output) /sck2 (input/output) /rxd2 (input) /txd2 (output) port a pins pin functions in mode 7 pa3 (input/output) pa2 (input/output) pa1 (input/output) pa0 (input/output)/a16 (output) /a19 (output) /a18 (output) /a17 (output) /sck2 (input/output) /rxd2 (input) /txd2 (output) pin functions in modes 4, 5, and 6 port a figure 9-6 port a pin functions 299 9.7.2 register configuration table 9-10 shows the port a register configuration. table 9-10 port a registers name abbreviation r/w initial value* 2 address* 1 port a data direction register paddr w h'0 h'fe39 port a data register padr r/w h'0 h'ff09 port a register porta r undefined h'ffb9 port a mos pull-up control register papcr r/w h'0 h'fe40 port a open-drain control register paodr r/w h'0 h'fe47 notes: *1 lower 16 bits of the address. *2 value of bits 3 to 0. (1) port a data direction register (paddr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit : initial value : r/w : paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. paddr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high- impedance when a transition is made to software standby mode. (a)modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, the corresponding port a pins are address outputs. when address output is disabled, setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. (b)mode 7 setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. 300 (2) port a data register (padr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit : initial value : r/w : padr is an 8-bit readable/writable register that stores output data for the port a pins (pa3 to pa0). bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. padr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port a register (porta) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r bit : initial value : r/w : note: * determined by the state of pins pa3 to pa0. porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa3 to pa0) must always be performed on padr. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its previous state after a manual reset and in software standby mode. 301 (4) port a mos pull-up control register (papcr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit : initial value : r/w : papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on a bit-by-bit basis. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. papcr is valid for port input and sci input pins. when a paddr bit is cleared to 0 (input port setting), setting the corresponding papcr bit to 1 turns on the mos input pull-up for the corresponding pin. papcr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (5) port a open-drain control register (paodr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit : initial value : r/w : paodr is an 8-bit readable/writable register that controls the pmos on/off status for each port a pin (pa3 to pa0). bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. paodr is valid for port output and sci output pins. setting a paodr bit to 1 makes the corresponding port a pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. paodr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.7.3 pin functions port a pins also function as sci2 i/o pins (txd2, rxd2, and sck2) and address output pins (a19 to a16). port a pin functions are shown in table 9-11. 302 table 9-11 port a pin functions pin pin functions and selection method pa3/a19/ sck2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa3ddr. operating mode modes 4 to 6 ae3 to ae0 11xx other than 11xx cke1 0 1 c/a 0 1 cke0 0 1 pa3ddr 0 1 pin function a19 output pa3 input pa3 output * sck2 output * sck2 output * sck2 input operating mode mode 7 ae3 to ae0 cke1 0 1 c/a 0 1 cke0 0 1 pa3ddr 0 1 pin function pa3 input pa3 output * sck2 output * sck2 output * sck2 input note: * nmos open-drain output when pa3odr = 1 in paodr. pa2/a18/ rxd2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa2ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 1011 or 11xx other than (1011 or 11xx) re 0101 pa2ddr 0 1 0 1 pin function a18 output pa2 input pa2 output * rxd2 input pa2 input pa2 output * rxd2 input note: * nmos open-drain output when pa2odr = 1 in paodr. 303 pin pin functions and selection method pa1/a17/ txd2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa1ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 101x or 11xx other than (101x or 11xx) te 0101 pa1ddr 0 1 0 1 pin function a17 output pa1 input pa1 output * txd2 output * pa1 input pa1 output * txd2 output * note: * nmos open-drain output when pa1odr = 1 in paodr. pa0/a16 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pa0ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 other than (0xxx or 1000) 0xxx or 1000 pa1ddr 0101 pin function a16 output pa0 input pa0 output * pa0 input pa0 output * note: * nmos open-drain output when pa0odr = 1 in paodr. 304 9.7.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. with port input and sci input pins, when a paddr bit is cleared to 0, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-12 summarizes the mos input pull-up states. table 9-12 mos input pull-up states (port a) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output, port output, sci output off off off off off port input, sci input off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off. 305 9.8 port b 9.8.1 overview port b is an 8-bit i/o port. port b pins also function as address bus outputs. the pin functions depend on the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 9-7 shows the port b pin configuration. pb7/a15 pb6/a14 pb5/a13 pb4/a12 pb3/a11 pb2/a10 pb1/a9 pb0/a8 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 /a15 (output) /a14 (output) /a13 (output) /a12 (output) /a11 (output) /a10 (output) /a9 (output) /a8 (output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) port b pins pin functions in modes 4, 5, and 6 pin functions in mode 7 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b figure 9-7 port b pin functions 306 9.8.2 register configuration table 9-13 shows the port b register configuration. table 9-13 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'fe3a port b data register pbdr r/w h'00 h'ff0a port b register portb r undefined h'ffba port b mos pull-up control register pbpcr r/w h'00 h'fe41 note: * lower 16 bits of the address. (1) port b data direction register (pbddr) 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit : initial value : r/w : pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a)modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, the corresponding port b pins are address outputs. when address output is disabled, setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. (b)mode 7 setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. 307 (2) port b data register (pbdr) 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit : initial value : r/w : pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port b register (portb) 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r bit : initial value : r/w : note: * determined by the state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its previous state after a manual reset and in software standby mode. (4) port b mos pull-up control register (pbpcr) 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit : initial value : r/w : pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on a bit-by-bit basis. pbpcr is valid for port input and tpu input pins. 308 when a pbddr bit is cleared to 0 (input port setting), setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pbpcr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.8.3 pin functions port b pins also function as address output pins (a15 to a8). port b pin functions are shown in table 9-14. table 9-14 port b pin functions pin pin functions and selection method pb7/a15 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb7ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'1xxx other than b'1xxx pb7ddr 0 1 pin function a15 output pb7 input pb7 output operating mode mode 7 ae3 to ae0 in pfcr pb7ddr 0 1 pin function pb7 input pb7 output 309 pin pin functions and selection method pb6/a14 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb6ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0111 or b'1xxx other than (b'0111 or b'1xxx) pb6ddr 0 1 pin function a14 output pb6 input pb6 output operating mode mode 7 ae3 to ae0 in pfcr pb6ddr 0 1 pin function pb6 input pb6 output pb5/a13 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb5ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'011x or b'1xxx other than (b'011x or b'1xxx) pb5ddr 0 1 pin function a13 output pb5 input pb5 output operating mode mode 7 ae3 to ae0 in pfcr pb5ddr 0 1 pin function pb5 input pb5 output 310 pin pin functions and selection method pb4/a12 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb4ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0100 or b'00xx other than (b'0100 or b'00xx) pb5ddr 0 1 pin function pb4 input pb4 output a12 output operating mode mode 7 ae3 to ae0 in pfcr pb4ddr 0 1 pin function pb4 input pb4 output pb3/a11 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb3ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'00xx other than b'00xx pb3ddr 0 1 pin function pb3 input pb3 output a11 output operating mode mode 7 ae3 to ae0 in pfcr pb3ddr 0 1 pin function pb3 input pb3 output 311 pin pin functions and selection method pb2/a10 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb2ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0010 or b'000x other than b'0010 or b'000x pb2ddr 0 1 pin function pb2 input pb2 output a10 output operating mode mode 7 ae3 to ae0 in pfcr pb2ddr 0 1 pin function pb2 input pb2 output pb1/a9 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pb1ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'000x other than b'000x pb1ddr 0 1 pin function pb1 input pb1 output a9 output operating mode mode 7 ae3 to ae0 in pfcr pb1ddr 0 1 pin function pb1 input pb1 output 312 pin pin functions and selection method pb0/a8 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, bit pb1ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0000 other than b'0000 p30ddr 0 1 pin function pb0 input pb0 output a8 output operating mode mode 7 ae3 to ae0 in pfcr pb0ddr 0 1 pin function pb0 input pb0 output 9.8.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. with port input pins, when a pbddr bit is cleared to 0, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-15 summarizes the mos input pull-up states. table 9-15 mos input pull-up states (port b) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output, port output off off off off off port input off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off. 313 9.9 port c 9.9.1 overview port c is an 8-bit i/o port. port c pins also function as address bus outputs. the pin functions depend on the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 9-8 shows the port c pin configuration. pc7/ a7 pc6/ a6 pc5/ a5 pc4/ a4 pc3/ a3 pc2/ a2 pc1/ a1 pc0/ a0 pc7 (input)/a7 (output) pc6 (input)/a6 (output) pc5 (input)/a5 (output) pc4 (input)/a4 (output) pc3 (input)/a3 (output) pc2 (input)/a2 (output) pc1 (input)/a1 (output) pc0 (input)/a0 (output) port c pins pin functions in mode 6 a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pin functions in modes 4 and 5 port c pin functions in mode 7 pc7 (input/output) pc6 (input/output) pc5 (input/output) pc4 (input/output) pc3 (input/output) pc2 (input/output) pc1 (input/output) pc0 (input/output) figure 9-8 port c pin functions 314 9.9.2 register configuration table 9-16 shows the port c register configuration. table 9-16 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe3b port c data register pcdr r/w h'00 h'ff0b port c register portc r undefined h'ffbb port c mos pull-up control register pcpcr r/w h'00 h'fe42 note: * lower 16 bits of the address. (1) port c data direction register (pcddr) 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit : initial value : r/w : pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a)modes 4 and 5 port c pins are address outputs regardless of the pcddr settings. (b)mode 6 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. (c)mode 7 setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. 315 (2) port c data register (pcdr) 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit : initial value : r/w : pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port c register (portc) 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r bit : initial value : r/w : note: * determined by the state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its previous state after a manual reset and in software standby mode. (4) port c mos pull-up control register (pcpcr) 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit : initial value : r/w : pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on a bit-by-bit basis. pcpcr is valid for port input (modes 6 and 7). 316 when a pcddr bit is cleared to 0 (input port setting), setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pcpcr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.9.3 pin functions in each mode (1) modes 4 and 5 in modes 4 and 5, port c pins function as address outputs automatically. port c pin functions in modes 4 and 5 are shown in figure 9-9. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) port c figure 9-9 port c pin functions (modes 4 and 5) 317 (2) mode 6 in mode 6, port c pins function as address outputs or input ports, and input or output can be specified bit by bit. setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 6 are shown in figure 9-10. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pc7 (input) pc6 (input) pc5 (input) pc4 (input) pc3 (input) pc2 (input) pc1 (input) pc0 (input) when pcddr = 1 when pcddr = 0 port c figure 9-10 port c pin functions (mode 6) (3) mode 7 in mode 7, port c functions as an i/o port, and input or output can be specified bit by bit. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 7 are shown in figure 9-11. pc7 (input/output) pc6 (input/output) pc5 (input/output) pc4 (input/output) pc3 (input/output) pc2 (input/output) pc1 (input/output) pc0 (input/output) port c figure 9-11 port c pin functions (mode 7) 318 9.9.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in modes 6 and 7, and can be specified as on or off for individual bits. with the port input pin function (modes 6 and 7), when a pcddr bit is cleared to 0, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-17 summarizes the mos input pull-up states. table 9-17 mos input pull-up states (port c) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output (modes 4 and 5), port output (modes 6 and 7) off off off off off port input (modes 6 and 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off. 319 9.10 port d 9.10.1 overview port d is an 8-bit i/o port. port d pins also function as data bus input/output pins. the pin functions depend on the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 9-12 shows the port d pin configuration. pd7/ d15 pd6/ d14 pd5/ d13 pd4/ d12 pd3/ d11 pd2/ d10 pd1/ d9 pd0/ d8 d15 (input/output) d14 (input/output) d13 (input/output) d12 (input/output) d11 (input/output) d10 (input/output) d9 (input/output) d8 (input/output) port d pin pin functions in modes 4 to 6 pd7 (input/output) pd6 (input/output) pd5 (input/output) pd4 (input/output) pd3 (input/output) pd2 (input/output) pd1 (input/output) pd0 ( in p ut/out p ut ) pin functions in mode 7 port d figure 9-12 port d pin functions 320 9.10.2 register configuration table 9-18 shows the port d register configuration. table 9-18 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe3c port d data register pddr r/w h'00 h'ff0c port d register portd r undefined h'ffbc port d mos pull-up control register pdpcr r/w h'00 h'fe43 note: * lower 16 bits of the address. (1) port d data direction register (pdddr) 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit : initial value : r/w : pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (a)modes 4 to 6 the input/output direction settings in pdddr are ignored, and port d pins automatically function as data input/output pins. (b)mode 7 setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. 321 (2) port d data register (pddr) 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit : initial value : r/w : pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port d register (portd) 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r bit : initial value : r/w : note: * determined by the state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its previous state after a manual reset and in software standby mode. (4) port d mos pull-up control register (pdpcr) 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit : initial value : r/w : pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on a bit-by-bit basis. 322 pdpcr is valid for port input pins (mode 7). when a pdddr bit is cleared to 0 (input port setting), setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.10.3 pin functions in each mode (1) modes 4 to 6 in modes 4 to 6, port d pins function as data input/output pins automatically. port d pin functions in modes 4 to 6 are shown in figure 9-13. d15 (input/output) d14 (input/output) d13 (input/output) d12 (input/output) d11 (input/output) d10 (input/output) d9 (input/output) d8 (input/output) port d figure 9-13 port d pin functions (modes 4 to 6) (2) mode 7 in mode 7, port d functions as an i/o port, and input or output can be specified bit by bit. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. port d pin functions in mode 7 are shown in figure 9-14. 323 pd7 (input/output) pd6 (input/output) pd5 (input/output) pd4 (input/output) pd3 (input/output) pd2 (input/output) pd1 (input/output) pd0 (input/output) port d figure 9-14 port d pin functions (mode 7) 9.10.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in mode 7, and can be specified as on or off for individual bits. with the port input pin function (mode 7), when a pdddr bit is cleared to 0, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-19 summarizes the mos input pull-up states. table 9-19 mos input pull-up states (port d) pins power-on reset hardware standby mode manual reset software standby mode in other operations data input/output (modes 4 to 6), port output (mode 7) off off off off off port input (mode 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off. 324 9.11 port e 9.11.1 overview port e is an 8-bit i/o port. port e pins also function as data bus input/output pins. the pin functions depend on the operating mode and on whether 8-bit or 16-bit bus mode is used. port e has a built-in mos input pull-up function that can be controlled by software. figure 9-15 shows the port e pin configuration. pe7/ d7 pe6/ d6 pe5/ d5 pe4/ d4 pe3/ d3 pe2/ d2 pe1/ d1 pe0/ d0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e pins pin functions in modes 4 to 6 pin functions in mode 7 (input/output)/d7 (input/output) (input/output)/d6 (input/output) (input/output)/d5 (input/output) (input/output)/d4 (input/output) (input/output)/d3 (input/output) (input/output)/d2 (input/output) (input/output)/d1 (input/output) (input/output)/d0 (input/output) pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 ( in p ut/out p ut ) port e figure 9-15 port e pin functions 325 9.11.2 register configuration table 9-20 shows the port e register configuration. table 9-20 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'fe3d port e data register pedr r/w h'00 h'ff0d port e register porte r undefined h'ffbd port e mos pull-up control register pepcr r/w h'00 h'fe44 note: * lower 16 bits of the address. (1) port e data direction register (peddr) 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit : initial value : r/w : peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value will be read. peddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (a)modes 4 to 6 when 8-bit bus mode is selected, port e functions as an i/o port. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction settings in peddr are ignored, and port e pins automatically function as data input/output pins. for details of the 8-bit and 16-bit bus modes, see section 6, bus controller. (b)mode 7 setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. 326 (2) port e data register (pedr) 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit : initial value : r/w : pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port e register (porte) 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r bit : initial value : r/w : note: * determined by the state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its previous state after a manual reset and in software standby mode. (4) port e mos pull-up control register (pepcr) 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit : initial value : r/w : pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on a bit-by-bit basis. pepcr is valid for port input pins (modes 4 to 6 in 8-bit bus mode, or mode 7). 327 when a peddr bit is cleared to 0 (input port setting), setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.11.3 pin functions in each mode (1) modes 4 to 6 in modes 4 to 6, if 8-bit access space is designated and 8-bit bus mode is selected, port e functions as an i/o port. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction settings in peddr are ignored, and port e pins function as data input/output pins. port e pin functions in modes 4 to 6 are shown in figure 9-16. pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 (input/output) d7 (input/output) d6 (input/output) d5 (input/output) d4 (input/output) d3 (input/output) d2 (input/output) d1 (input/output) d0 (input/output) 8-bit bus mode port e 16-bit bus mode figure 9-16 port e pin functions (modes 4 to 6) 328 (2) mode 7 in mode 7, port e functions as an i/o port, and input or output can be specified bit by bit. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. port e pin functions in mode 7 are shown in figure 9-17. pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 (input/output) port e figure 9-17 port e pin functions (mode 7) 9.11.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in modes 4 to 6 in 8-bit bus mode, or in mode 7, and can be specified as on or off for individual bits. with the port input pin function (modes 4 to 6 in 8-bit bus mode, or mode 7), when a peddr bit is cleared to 0, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-21 summarizes the mos input pull-up states. 329 table 9-21 mos input pull-up states (port e) pins power-on reset hardware standby mode manual reset software standby mode in other operations data input/output (modes 4 to 6 with 16-bit bus), port output (modes 4 to 6 with 8-bit bus, mode 7) off off off off off port input (modes 4 to 6 with 8-bit bus, mode 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off. 330 9.12 port f 9.12.1 overview port f is an 8-bit i/o port. port f pins also function as external interrupt input pins ( irq2 and irq3 ), bus control signal i/o pins ( as , rd , hwr , lwr , wait , breq , and back ), and the system clock (?) output pin. the interrupt input pins ( irq2 and irq3 ) are schmitt-triggered inputs. figure 9-18 shows the port f pin configuration. pf7/ ? pf6/ as pf5/ rd pf4/ hwr pf3/ lwr / irq3 pf2/ wait pf1/ back pf0/ breq / i rq2 port f pins port f pf7 (input)/? (output) pf6 (input/output) pf5 (input/output) pf4 (input/output) pf3 (input/output)/ irq3 (input) pf2 (input/output) pf1 (input/output) pf0 (input/output)/ irq2 (input) pin functions in mode 7 pf7 (input)/? (output) as (output) rd (output) hwr (output) pf3 (input/output)/ lwr (output)/ irq3 (input) pf2 (input/output)/ wait (input) pf1 (input/output)/ back (output) pf0 (input/output)/ breq (input)/ irq2 (input) pin functions in modes 4 to 6 figure 9-18 port f pin functions 331 9.12.2 register configuration table 9-22 shows the port f register configuration. table 9-22 port f registers name abbreviation r/w initial value address* 1 port f data direction register pfddr w h'80/h'00* 2 h'fe3e port f data register pfdr r/w h'00 h'ff0e port f register portf r undefined h'ffbe notes: *1 lower 16 bits of the address. *2 initial value depends on the mode. initialized to h'80 in modes 4 to 6, and to h'00 in mode 7. (1) port f data direction register (pfddr) 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit : modes 4 to 6 : initial value : r/w : mode 7 : initial value : r/w : pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read.. pfddr is initialized to h'80 (modes 4 to 6) or h'00 (mode 7) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a)modes 4 to 6 pin pf7 functions as the ? output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. the input/output direction specification in pfddr is ignored for pins pf6 to pf3, which are automatically designated as bus control outputs ( as , rd , hwr , and lwr ). pins pf2 to pf0 are made bus control input/output pins ( wait , back , and breq ) by bus controller settings. otherwise, setting a pfddr bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 332 (b)mode 7 setting a pfddr bit to 1 makes the corresponding port f pin pf6 to pf0 an output port, or in the case of pin pf7, the ? output pin. clearing the bit to 0 makes the pin an input port. (2) port f data register (pfdr) 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit : initial value : r/w : pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf0). pfdr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port f register (portf) 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r bit : initial value : r/w : note: * determined by the state of pins pf7 to pf0. portf is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port f pins (pf7 to pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its previous state after a manual reset and in software standby mode. 9.12.3 pin functions port f pins also function as external interrupt input pins ( irq2 and irq3 ), bus control signal i/o pins ( as , rd , hwr , lwr , wait , breq , and back ), and the system clock (?) output pin. the pin functions differ between modes 4 to 6 and mode 7. port f pin functions are shown in table 9- 23. 333 table 9-23 port f pin functions pin pin functions and selection method pf7/? the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input ? output pf6/ as the pin function is switched as shown below according to the operating mode and bit pf6ddr. operating mode modes 4 to 6 mode 7 pf6ddr 0 1 pin function as output pf6 input pf6 output pf5/ rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 4 to 6 mode 7 pf5ddr 0 1 pin function rd output pf5 input pf5 output pf4/ hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 4 to 6 mode 7 pf4ddr 0 1 pin function hwr output pf4 input pf4 output pf3/ lwr / irq3 the pin function is switched as shown below according to the operating mode, the bus mode, and bit pf3ddr. operating mode modes 4 to 6 mode 7 bus mode 16-bit bus mode 8-bit bus mode pf3ddr 0101 pin function lwr output pf3 input pf3 output pf3 input pf3 output irq3 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function. 334 pin pin functions and selection method pf2/ wait the pin function is switched as shown below according to the operating mode, bit waite, and bit pf2ddr. operating mode modes 4 to 6 mode 7 waite 0 1 pf2ddr 0 1 0 1 pin function pf2 input pf2 output wait input pf2 input pf2 output pf1/ back / buzz the pin function is switched as shown below according to the operating mode, bit brle, bit buzze in pfcr, and bit pf1ddr. operating mode modes 4 to 6 mode 7 brle 0 1 pf1ddr 0 1 0 1 pin function pf1 input pf1 output back output pf1 input pf1 output pf0/ breq / irq2 the pin function is switched as shown below according to the operating mode, bit brle, and bit pf0ddr. operating mode modes 4 to 6 mode 7 brle 0 1 pf0ddr 0 1 0 1 pin function pf0 input pf0 output breq input pf0 input pf0 output irq2 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function. 335 9.13 port g 9.13.1 overview port g is a 5-bit i/o port. port g pins also function as external interrupt input pins ( irq6 and irq7 ) and bus control signal output pins ( cs0 to cs3 ). the interrupt input pins ( irq6 and irq7 ) are schmitt-triggered inputs. figure 9-19 shows the port g pin configuration. pg4/ cs0 pg3/ cs1 pg2/ cs2 pg1/ cs3/ irq7 pg0/ irq6 pg4 (input/output) pg3 (input/output) pg2 (input/output) pg1 (input/output)/ irq7 (input) pg0 (input/output)/ irq6 (input) port g pins pin functions in mode 7 pin functions in modes 4 to 6 pg4 (input)/cs0 (output) pg3 (input)/cs1 (output) pg2 (input)/cs2 (output) pg1 (input)/cs3 (output)/irq7 (input) pg0 (input/output)/ irq6 (input) port g figure 9-19 port g pin functions 336 9.13.2 register configuration table 9-24 shows the port g register configuration. table 9-24 port g registers name abbreviation r/w initial value* 2 address* 1 port g data direction register pgddr w h'10/h'00* 3 h'fe3f port g data register pgdr r/w h'00 h'ff0f port g register portg r undefined h'ffbf notes: *1 lower 16 bits of the address. *2 value of bits 4 to 0. *3 initial value depends on the mode. initialized to h'10 in modes 4 and 5, and to h'00 in modes 6 and 7. (1) port g data direction register (pgddr) 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit : modes 4 and 5 : initial value : r/w : modes 6 and 7 : initial value : r/w : pgddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port g. pgddr cannot be read. also, bits 7 to 5 are reserved, and will return an undefined value if read. bit pg4ddr is initialized to 1 (modes 4 and 5) or 0 (modes 6 and 7) by a power-on reset and in hardware standby mode. pgddr retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a)modes 4 to 6 pins pg4 to pg1 function as bus control signal output pins ( cs0 to cs3 ) when the corresponding pgddr bits are set to 1, and as input ports when the bits are cleared to 0. pin pg0 functions as an output port when the corresponding pgddr bit is set to 1, and as an input port when the bit is cleared to 0. 337 (b)mode 7 setting a pgddr bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. (2) port g data register (pgdr) 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit : initial value : r/w : pgdr is an 8-bit readable/writable register that stores output data for the port g pins (pg4 to pg0). bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read. pgdr is initialized to h'00 (bits 4 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port g register (portg) 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r bit : initial value : r/w : note: * determined by the state of pins pg4 to pg0. portg is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port g pins (pg4 to pg0) must always be performed on pgdr. bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read. if a port g read is performed while pgddr bits are set to 1, the pgdr values are read. if a port g read is performed while pgddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portg contents are determined by the pin states, as pgddr and pgdr are initialized. portg retains its previous state after a manual reset and in software standby mode. 338 9.13.3 pin functions port g pins also function as external interrupt input pins ( irq6 and irq7 ) and bus control signal output pins ( cs0 to cs3 ). the pin functions differ between modes 4 to 6 and mode 7. port g pin functions are shown in table 9-25. table 9-25 port g pin functions pin pin functions and selection method pg4/ cs0 the pin function is switched as shown below according to the operating mode and bit pg4ddr. operating mode modes 4 to 6 mode 7 pg4ddr 0101 pin function pg4 input cs0 output pg4 input pg4 output pg3/ cs1 the pin function is switched as shown below according to the operating mode and bit pg3ddr. operating mode modes 4 to 6 mode 7 pg3ddr 0101 pin function pg3 input cs1 output pg3 input pg3 output pg2/ cs2 the pin function is switched as shown below according to the operating mode and bit pg2ddr. operating mode modes 4 to 6 mode 7 pg2ddr 0101 pin function pg2 input cs2 output pg2 input pg2 output pg1/ cs3 / irq7 the pin function is switched as shown below according to the operating mode and bit pg1ddr. operating mode modes 4 to 6 mode 7 pg1ddr 0101 pin function pg1 input cs3 output pg1 input pg1 output irq7 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function. 339 pin pin functions and selection method pg0/ irq6 the pin function is switched as shown below according to bit pg0ddr. pg0ddr 0 1 pin function pg0 input pg0 output irq6 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function. 340 341 section 10 16-bit timer pulse unit (tpu) 10.1 overview the h8s/2214 has an on-chip 16-bit timer pulse unit (tpu) comprising three 16-bit timer channels. 10.1.1 features ? can input/output a maximum of 8 pulses ? a total of 8 timer general registers (tgrs) are provided (four each for channel 0, and two each for channels 1and 2), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channel 0 can also be used as buffer registers ? selection of 8 counter input clocks for each channel ? the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set maximum of 7-phase pwm output possible by combination with synchronous operation ? buffer operation settable for channel 0 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible ? phase counting mode settable independently for each of channels 1and 2 ? two-phase encoder pulse up/down-count possible ? sci0 baud rate clock generation by channels 1 and 2 ? an sci0 baud rate clock can be generated using an and circuit for tioca1 output and tioca2 output ? fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface 342 ? 13 interrupt sources ? for channel 0, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1 and 2 two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently ? automatic transfer of register data ? block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (dtc) and dma controller (dmac) activation ? module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. table 10-1 lists the functions of the tpu. 343 table 10-1 tpu functions item channel 0 channel 1 channel 2 count clock ?/1 ?/4 ?/16 ?/64 tclka tclkb tclkc tclkd ?/1 ?/4 ?/16 ?/64 ?/256 tclka tclkb ?/1 ?/4 ?/16 ?/64 ?/1024 tclka tclkb tclkc general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b general registers/ buffer registers tgr0c tgr0d i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture compare 0 output match 1 output output toggle output input capture function synchronous operation pwm mode phase counting mode buffer operation dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture dmac activation tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture legend : possible : not possible 344 item channel 0 channel 1 channel 2 interrupt sources 5 sources ? compare match or input capture 0a ? compare match or input capture 0b ? compare match or input capture 0c ? compare match or input capture 0d ? overflow 4 sources ? compare match or input capture 1a ? compare match or input capture 1b ? overflow ? underflow 4 sources ? compare match or input capture 2a ? compare match or input capture 2b ? overflow ? underflow 345 10.1.2 block diagram figure 10-1 shows a block diagram of the tpu. control logic tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr clock input ?/1 ?/4 ?/16 ?/64 ?/256 ?/1024 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 0: channel 1: channel 2: internal data bus tiorl module data bus tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u internal clock: external clock: channel 0: channel 1: channel 2: channel 2 common bus interface legend tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) sck0 (to sci0) figure 10-1 block diagram of h8s/2214 tpu 346 10.1.3 pin configuration table 10-2 summarizes the tpu pins. table 10-2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 phase counting mode b phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin 347 10.1.4 register configuration table 10-3 summarizes the tpu registers. table 10-3 tpu registers channel name abbreviation r/w initial value address* 1 0 timer control register 0 tcr0 r/w h'00 h'ff10 timer mode register 0 tmdr0 r/w h'c0 h'ff11 timer i/o control register 0h tior0h r/w h'00 h'ff12 timer i/o control register 0l tior0l r/w h'00 h'ff13 timer interrupt enable register 0 tier0 r/w h'40 h'ff14 timer status register 0 tsr0 r/(w)* 2 h'c0 h'ff15 timer counter 0 tcnt0 r/w h'0000 h'ff16 timer general register 0a tgr0a r/w h'ffff h'ff18 timer general register 0b tgr0b r/w h'ffff h'ff1a timer general register 0c tgr0c r/w h'ffff h'ff1c timer general register 0d tgr0d r/w h'ffff h'ff1e 1 timer control register 1 tcr1 r/w h'00 h'ff20 timer mode register 1 tmdr1 r/w h'c0 h'ff21 timer i/o control register 1 tior1 r/w h'00 h'ff22 timer interrupt enable register 1 tier1 r/w h'40 h'ff24 timer status register 1 tsr1 r/(w)* 2 h'c0 h'ff25 timer counter 1 tcnt1 r/w h'0000 h'ff26 timer general register 1a tgr1a r/w h'ffff h'ff28 timer general register 1b tgr1b r/w h'ffff h'ff2a 2 timer control register 2 tcr2 r/w h'00 h'ff30 timer mode register 2 tmdr2 r/w h'c0 h'ff31 timer i/o control register 2 tior2 r/w h'00 h'ff32 timer interrupt enable register 2 tier2 r/w h'40 h'ff34 timer status register 2 tsr2 r/(w)* 2 h'c0 h'ff35 timer counter 2 tcnt2 r/w h'0000 h'ff36 timer general register 2a tgr2a r/w h'ffff h'ff38 timer general register 2b tgr2b r/w h'ffff h'ff3a 348 channel name abbreviation r/w initial value address* 1 all timer start register tstrr/w h'00 h'feb0 timer synchro register tsyrr/w h'00 h'feb1 module stop control register a mstpcra r/w h'3f h'fde8 notes: *1 lower 16 bits of the address. *2 can only be written with 0 for flag clearing. 10.2 register descriptions 10.2.1 timer control register (tcr) 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : channel 0: tcr0 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w channel 1: tcr1 channel 2: tcr2 bit initial value r/w : : : the tcr registers are 8-bit registers that control the tcnt channels. the tpu has three tcr registers, one for each of channels 0 to 2. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode. 349 bits 7 to 5counter clear 2 to 0 (cclr2 to cclr0): these bits select the tcnt counter clearing source. bit 7 bit 6 bit 5 channel cclr2 cclr1 cclr0 description 0000 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture* 2 1 0 tcnt cleared by tgrd compare match/input capture* 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operatio* 1 bit 7 bit 6 bit 5 channel reserved* 3 cclr1 cclr0 description 1, 2 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation* 1 notes: *1 synchronous operation setting is performed by setting the sync bit in tsyr to 1. *2 when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. *3 bit 7 is reserved in channels 1 and 2. it is always read as 0 and cannot be modified. 350 bits 4 and 3clock edge 1 and 0 (ckeg1, ckeg0): these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. ?/4 both edges = ?/2 rising edge). if phase counting mode is used on channels 1 and 2, this setting is ignored and the phase counting mode setting has priority. bit 4 bit 3 ckeg1 ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 count at both edges note: internal clock edge selection is valid when the input clock is ?/4 or slower. this setting is ignored if the input clock is ?/1, or when overflow/underflow of another channel is selected. bits 2 to 0time prescaler 2 to 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 10-4 shows the clock sources that can be set for each channel. table 10-4 tpu clock sources channel internal clock external clock channel ?/1 ?/4 ?/16 ?/64 ?/256 ?/1024 ?/4096 tclka tclkb tclkc tclkd 0 1 2 legend : setting blank : no setting bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 0000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input 351 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 1000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on ?/256 1 setting prohibited note: this setting is ignored when channel 1 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 2000 internal clock: counts on ?/1 (initial value) 1 internal clock: counts on ?/4 1 0 internal clock: counts on ?/16 1 internal clock: counts on ?/64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on ?/1024 note: this setting is ignored when channel 2 is in phase counting mode. 352 10.2.2 timer mode register (tmdr) 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 0: tmdr0 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 1: tmdr1 channel 2: tmdr2 the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has three tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode. bits 7 and 6reserved: read-only bits, always read as 1. bit 5buffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1 and 2 which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd used together for buffer operation bit 4buffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. 353 in channels 1 and 2 which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc used together for buffer operation bits 3 to 0modes 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3 bit 2 bit 1 bit 0 md3* 1 md2* 2 md1 md0 description 0000 normal operation (initial value) 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** * : dont care notes: *1 md3 is a reserved bit. in a write, it should always be written with 0. *2 phase counting mode cannot be set for channel 0. in this case, 0 should always be written to md2. 354 10.2.3 timer i/o control register (tior) 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : channel 0: tior0h channel 1: tior1 channel 2: tior2 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w channel 0: tior0l note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. bit initial value r/w : : : the tior registers are 8-bit registers that control the tgr registers. the tpu has four tior registers, two each for channel 0, and one each for channels 1 and 2. the tior registers are initialized to h'00 by a reset, and in hardware standby mode. care is required since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified. 355 bits 7 to 4 i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): bits iob3 to iob0 specify the function of tgrb. bits iod3 to iod0 specify the function of tgrd. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 0 000 1 0 1 0 1 tgr0b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0b is input capture register capture input source is tiocb0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care 356 bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 0 000 1 0 1 0 1 tgr0d is output compare register* 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0d is input capture register* 1 capture input source is tiocd0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care note: *1 when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 1 000 1 0 1 0 1 tgr1b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 0 0 1 0 1 * tgr1b is input capture register capture input source is tiocb1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care 357 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 2 000 1 0 1 0 1 tgr2b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2b is input capture register capture input source is tiocb2 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care 358 bits 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 0 000 1 0 1 0 1 tgr0a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0a is input capture register capture input source is tioca0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care 359 bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 0 000 1 0 1 0 1 tgr0c is output compare register* 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0c is input capture register* 1 capture input source is tiocc0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care note: *1 when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 360 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 1 000 1 0 1 0 1 tgr1a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr1a is input capture register capture input source is tioca1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** setting prohibited * : dont care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 2 000 1 0 1 0 1 tgr2a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2a is input capture register capture input source is tioca2 pin input capture at rising edge input capture at falling edge input capture at both edges * : dont care 361 10.2.4 timer interrupt enable register (tier) 7 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : channel 0: tier0 7 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w channel 1: tier1 channel 2: tier2 bit initial value r/w : : : the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has three tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode. bit 7reserved: only 0 should be written to this bit. bit 6reserved: read-only bit, always read as 1. bit 5underflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1 and 2. in channel 0, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled 362 bit 4overflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. bit 4 tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3tgr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channel 0. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled bit 2tgr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channel 0. in channels 1 and 2, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1tgr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. bit 1 tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled 363 bit 0tgr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. bit 0 tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled 10.2.5 timer status register (tsr) 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value r/w : : : channel 0: tsr0 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * channel 1: tsr1 channel 2: tsr2 bit initial value r/w note: * can only be written with 0 for flag clearing. : : : the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has three tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode. bit 7count direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1 and 2. in channel 0, bit 7 is reserved. it is always read as 1 and cannot be modified. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value) 364 bit 6reserved: read-only bit, always read as 1 and cannot be modified. bit 5underflow flag (tcfu): status flag that indicates that tcnt underflow has occurred when channels 1and 2 are set to phase counting mode. in channel 0, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcfu description 0 [clearing condition] (initial value) when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4overflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4 tcfv description 0 [clearing condition] (initial value) when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) bit 3input capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channel 0. in channels 1 and 2, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgfd description 0 [clearing conditions] (initial value) ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register bit 2input capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channel 0. 365 in channels 1and 2, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgfc description 0 [clearing conditions] (initial value) ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register bit 1input capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1 tgfb description 0 [clearing conditions] (initial value) ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register 366 bit 0input capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0 tgfa description 0 [clearing conditions] (initial value) ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when dmac is activated by tgia interrupt while dta bit of dmabcr in dmac is 1 ? when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register 10.2.6 timer counter (tcnt) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter * ) channel 2: tcnt2 (up/down-counter * ) note : * these counters can be used as up/down-counters only in phase counting mode. in other cases they function as up-counters. the tcnt registers are 16-bit counters. the tpu has three tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 367 10.2.7 timer general register (tgr) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has eight tgr registers, four each for channel 0 and two each for channels 1 and 2. tgrc and tgrd for channel 0 can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgratgrc and tgrbtgrd. 10.2.8 timer start register (tstr) 7 0 6 0 5 0 4 0 3 0 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value r/w : : : tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 2. tstr is initialized to h'00 by a reset, and in hardware standby mode. tcnt counter operation must be halted before setting the operating mode in tmdr, or setting the tcnt count clock in tcr. bits 7 to 3reserved: should always be written with 0. 368 bits 2 to 0counter start 2 to 0 (cst2 to cst0): these bits select operation or stoppage for tcnt. bit n cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation (n = 2 to 0) note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. 10.2.9 timer synchro register (tsyr) 7 0 6 0 5 0 4 0 3 0 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w : : : tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channels 0 to 2 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 to 3reserved: should always be written with 0. bits 2 to 0timer synchro 2 to 0 (sync2 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels* 1 , and synchronous clearing through counter clearing on another channel* 2 are possible. notes: *1 to set synchronous operation, the sync bits for at least two channels must be set to 1. *2 to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 369 bit n syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible (n = 2 to 0) 10.2.10 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value r/w : : : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is a 16-bit readable/writable register that performs module stop mode control. when the mstpa5 bit in mstpcr is set to 1, tpu operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 20.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 5module stop (mstpa5): specifies the tpu module stop mode. bit 5 mstpa5 description 0 tpu module stop mode cleared 1 tpu module stop mode set (initial value) 370 10.3 interface to bus master 10.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 10-2. bus interface h internal data bus l bus master module data bus tcnth tcntl figure 10-2 16-bit register access operation [bus master ? tcnt (16 bits)] 10.3.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units. examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. bus interface h internal data bus l module data bus tcr bus master figure 10-3 8-bit register access operation [bus master ? tcr (upper 8 bits)] 371 bus interface h internal data bus l module data bus tmdr bus master figure 10-4 8-bit register access operation [bus master ? tmdr (lower 8 bits)] bus interface h internal data bus l module data bus tcrtmdr bus master figure 10-5 8-bit register access operation [bus master ? tcr and tmdr (16 bits)] 372 10.4 operation 10.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. synchronous operation: when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. buffer operation ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. ? when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. pwm mode: in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. phase counting mode: in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1 and 2. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this can be used for two-phase encoder pulse input. 373 10.4.2 basic functions counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. ? example of count operation setting procedure figure 10-6 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count operation 374 ? free-running count operation and periodic count operation immediately after a reset, the tpus tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 10-7 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 10-7 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000. 375 figure 10-8 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 10-8 periodic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. ? example of setting procedure for waveform output by compare match figure 10-9 shows an example of the setting procedure for waveform output by compare match. select waveform output mode output selection set output timing start count operation 376 ? examples of waveform output operation figure 10-10 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 10-10 example of 0 output/1 output operation figure 10-11 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 10-11 example of toggle output operation 377 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. ? example of input capture operation setting procedure figure 10-12 shows an example of the input capture operation setting procedure. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 10-12 example of input capture operation setting procedure 378 ? example of input capture operation figure 10-13 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 10-13 example of input capture operation 379 10.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 2 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 10-14 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting 380 example of synchronous operation: figure 10-15 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchronous clearing by tgr0b compare match, is performed for channel 0 to 2 tcnt counters, and the data set in tgr0b is used as the pwm cycle. for details of pwm modes, see section 10.4.5, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 10-15 example of synchronous operation 381 10.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10-5 shows the register combinations used in buffer operation. table 10-5 register combinations in buffer operation channel timer general register buffer register 0 tgr0a tgr0c tgr0b tgr0d ? when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10-16. buffer register timer general register tcnt comparator compare match signal figure 10-16 compare match buffer operation 382 ? when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10-17. buffer register timer general register tcnt input capture signal figure 10-17 input capture buffer operation example of buffer operation setting procedure: figure 10-18 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count 383 examples of buffer operation ? when tgr is an output compare register figure 10-19 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 10.4.5, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 10-19 example of buffer operation (1) 384 ? when tgr is an input capture register figure 10-20 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 10-20 example of buffer operation (2) 385 10.4.5 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. ? pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob3 to iob0 and iod3 to iod0 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 4-phase pwm output is possible. ? pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 7-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 10-6. 386 table 10-6 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioca0 tioca0 tgr0b tiocb0 tgr0c tiocc0 tiocc0 tgr0d tiocd0 1 tgr1a tioca1 tioca1 tgr1b tiocb1 2 tgr2a tioca2 tioca2 tgr2b tiocb2 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set. example of pwm mode setting procedure: figure 10-21 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level 387 examples of pwm mode operation: figure 10-22 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in tgrb registers as the duty. tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10-22 example of pwm mode operation (1) figure 10-23 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgr0a to tgr0d, tgr1a), to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgrs as the duty. 388 tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 10-23 example of pwm mode operation (2) 389 figure 10-24 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 10-24 example of pwm mode operation (3) 390 10.4.6phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1and 2. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag provides an indication of whether tcnt is counting up or down. table 10-7 shows the correspondence between external clock pins and channels. table 10-7 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 is set to phase counting mode tclka tclkb when channel 2 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 10-25 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count 391 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. ? phase counting mode 1 figure 10-26 shows an example of phase counting mode 1 operation, and table 10-8 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 10-26 example of phase counting mode 1 operation table 10-8 up/down-count conditions in phase counting mode 1 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level high level high level down-count low level high level low level legend : rising edge : falling edge 392 ? phase counting mode 2 figure 10-27 shows an example of phase counting mode 2 operation, and table 10-9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) figure 10-27 example of phase counting mode 2 operation table 10-9 up/down-count conditions in phase counting mode 2 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level dont care low level dont care low level dont care high level up-count high level dont care low level dont care high level dont care low level down-count legend : rising edge : falling edge 393 ? phase counting mode 3 figure 10-28 shows an example of phase counting mode 3 operation, and table 10-10 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) down-count figure 10-28 example of phase counting mode 3 operation table 10-10 up/down-count conditions in phase counting mode 3 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level dont care low level dont care low level dont care high level up-count high level down-count low level dont care high level dont care low level dont care legend : rising edge : falling edge 394 ? phase counting mode 4 figure 10-29 shows an example of phase counting mode 4 operation, and table 10-11 summarizes the tcnt up/down-count conditions. time tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) up-count down-count tcnt value figure 10-29 example of phase counting mode 4 operation table 10-11 up/down-count conditions in phase counting mode 4 tclka (channel 1) tclkc (channel 2) tclkb (channel 1) tclkd (channel 2) operation high level up-count low level low level dont care high level high level down-count low level high level dont care low level legend : rising edge : falling edge 395 10.5 interrupts 10.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 5, interrupt controller. table 10-12 lists interrupt sources and dma controller (dmac) and data transfer controller (dtc) activation. table 10-12 interrupt sources and dma controller (dmac) and data transfer (dtc) activation channel interrupt source description dmac activation dtc activation priority 0 tgi0a tgr0a input capture/compare match possible possible high tgi0b tgr0b input capture/compare match not possible possible tgi0c tgr0c input capture/compare match not possible possible tgi0d tgr0d input capture/compare match not possible possible tci0v tcnt0 overflow not possible not possible 1 tgi1a tgr1a input capture/compare match possible possible tgi1b tgr1b input capture/compare match not possible possible tci1v tcnt1 overflow not possible not possible tci1u tcnt1 underflow not possible not possible 2 tgi2a tgr2a input capture/compare match possible possible tgi2b tgr2b input capture/compare match not possible possible tci2v tcnt2 overflow not possible not possible tci2u tcnt2 underflow not possible not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. 396 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has eight input capture/compare match interrupts, four for channel 0, and two each for channels 1 and 2. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has three overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has two overflow interrupts, one each for channels 1 and 2. 10.5.2 dtc activation dtc activation: the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 8, data transfer controller (dtc). a total of eight tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channel 0, and two each for channels 1 and 2. dmac activation: the dmac can be activated by the tgra input capture/compare match interrupt for a channel. for details, see section 7, dma controller (dmac). with the tpu, a total of three tgra input capture/compare match interrupts can be used as dmac activation sources, one for each channel. 397 10.6 operation timing 10.6.1 input/output timing tcnt count timing: figure 10-30 shows tcnt count timing in internal clock operation, and figure 10-31 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock ? nC1 n n+1 n+2 falling edge rising edge figure 10-30 count timing in internal clock operation tcnt tcnt input clock external clock ? nC1 n n+1 n+2 rising edge falling edge falling edge figure 10-31 count timing in external clock operation 398 output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 10-32 shows output compare output timing. tgr tcnt tcnt input clock ? n n n+1 compare match signal tioc pin figure 10-32 output compare output timing input capture signal timing: figure 10-33 shows input capture signal timing. tcnt input capture input ? n n+1 n+2 n n+2 tgr input capture signal figure 10-33 input capture input signal timing 399 timing for counter clearing by compare match/input capture: figure 10-34 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-35 shows the timing when counter clearing by input capture occurrence is specified. tcnt counter clear signal compare match signal ? tgr n n h'0000 figure 10-34 counter clear timing (compare match) tcnt counter clear signal input capture signal ? tgr n h'0000 n figure 10-35 counter clear timing (input capture) 400 buffer operation timing: figures 10-36 and 10-37 show the timing in buffer operation. tgra, tgrb compare match signal tcnt ? tgrc, tgrd nn n n n+1 figure 10-36 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal ? tgrc, tgrd n n n n+1 n n n+1 figure 10-37 buffer operation timing (input capture) 401 10.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10-38 shows the timing for setting of the tgf flag in tsr by compare match occurrence, and tgi interrupt request signal timing. tgr tcnt tcnt input clock ? n n n+1 compare match signal tgf flag tgi interrupt figure 10-38 tgi interrupt timing (compare match) 402 tgf flag setting timing in case of input capture: figure 10-39 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and tgi interrupt request signal timing. tgr tcnt input capture signal ? n n tgf flag tgi interrupt figure 10-39 tgi interrupt timing (input capture) 403 tcfv flag/tcfu flag setting timing: figure 10-40 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and tciv interrupt request signal timing. figure 10-41 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock ? h'ffff h'0000 tcfv flag tciv interrupt figure 10-40 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock ? h'0000 h'ffff tcfu flag tciu interrupt figure 10-41 tciu interrupt setting timing 404 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc or dmac is activated, the flag is cleared automatically. figure 10-42 shows the timing for status flag clearing by the cpu, and figure 10-43 shows the timing for status flag clearing by the dtc or dmac. status flag write signal address ? tsr address interrupt request signal tsr write cycle t1 t2 figure 10-42 timing for status flag clearing by cpu interrupt request signal status flag address ? source address dtc/dmac read cycle t1 t2 destination address t1 t2 dtc/dmac write cycle figure 10-43 timing for status flag clearing by dtc/dmac activation 405 10.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. input clock restrictions: the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10-44 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 10-44 phase difference, overlap, and pulse width in phase counting mode caution on period setting: when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = ? (n + 1) where f : counter frequency ? : operating frequency n : tgr set value 406 contention between tcnt write and clear operations: if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10-45 shows the timing in this case. counter clear signal write signal address ? tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 10-45 contention between tcnt write and clear operations 407 contention between tcnt write and increment operations: if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10-46 shows the timing in this case. tcnt input clock write signal address ? tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 10-46 contention between tcnt write and increment operations 408 contention between tgr write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the same value as before is written. figure 10-47 shows the timing in this case. compare match signal write signal address ? tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n+1 inhibited figure 10-47 contention between tgr write and compare match 409 contention between buffer register write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the data prior to the write. figure 10-48 shows the timing in this case. compare match signal write signal address ? buffer register address buffer register tgr write cycle t1 t2 n tgr n m buffer register write data figure 10-48 contention between buffer register write and compare match 410 contention between tgr read and input capture: if the input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 10-49 shows the timing in this case. input capture signal read signal address ? tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 10-49 contention between tgr read and input capture 411 contention between tgr write and input capture: if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10-50 shows the timing in this case. input capture signal write signal address ? tcnt tgr write cycle t1 t2 m tgr m tgr address figure 10-50 contention between tgr write and input capture 412 contention between buffer register write and input capture: if the input capture signal is generated in the t2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10-51 shows the timing in this case. input capture signal write signal address ? tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 10-51 contention between buffer register write and input capture 413 contention between overflow/underflow and counter clearing: if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 10-52 shows the operation timing when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt input clock ? tcnt tgf disabled tcfv h'ffff h'0000 figure 10-52 contention between overflow and counter clearing 414 contention between tcnt write and overflow/underflow: if there is an up-count or down- count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set . figure 10-53 shows the operation timing when there is contention between tcnt write and overflow. write signal address ? tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag disabled figure 10-53 contention between tcnt write and overflow multiplexing of i/o pins: in the h8s/2214, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. interrupts and module stop mode: if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source, dtc activation source, or dmac activation source. interrupts should therefore be disabled before entering module stop mode. 415 section 11 watchdog timer (wdt) 11.1 overview the h8s/2214 has an on-chip watchdog timer/watch timer with one channel. the watchdog timer can generate an internal interrupt or an internal reset signal if a system crash prevents the cpu from writing to the counter, allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer mode, an interval timer interrupt is generated each time the counter overflows. 11.1.1 features wdt features are listed below. ? switchable between watchdog timer mode and interval timer mode ? internal reset or internal interrupt generated when watchdog timer mode choice of whether or not an internal reset (power-on reset or manual reset selectable) is effected when the counter overflows ? interrupt generation in interval timer mode ? an interval timer interrupt is generated when the counter overflows ? choice of 8 counter input clocks ? maximum wdt interval: system clock period 131072 256 416 11.1.2 block diagram figure 11-1 shows block diagrams of wdt. overflow wovi0 (interrupt request signal) internal reset signal * tcnt rstcsr tcsr ?/2 ?/64 ?/128 ?/512 ?/2048 ?/8192 ?/32768 ?/131072 clock clock select internal clock bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register note: * the internal reset signal can be generated by means of a register setting. either a power-on reset or a manual reset can be selected. interrupt control reset control figure 11-1 block diagram of wdt 417 11.1.3 register configuration the wdt has three registers, as summarized in table 11-1. these registers control clock selection, wdt mode switching, the reset signal, etc. table 11-1 wdt registers address* 1 name abbreviation r/w initial value write* 2 read timer control/status register tcsr0 r/(w)* 3 h'00 h'ff74 h'ff74 timer counter tcnt0 r/w h'00 h'ff74 h'ff75 reset control/status register rstcsr0 r/(w)* 3 h'1f h'ff76 h'ff77 notes: *1 lower 16 bits of the address. *2 for details of write operations, see section 11.2.4, notes on register access. *3 only 0 can be written in bit 7, to clear the flag. 418 11.2 register descriptions 11.2.1 timer counter (tcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit : initial value : r/w : tcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf flag in tcsr is set to 1. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * tcnt is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. 11.2.2 timer control/status register (tcsr) 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit : initial value : r/w : note: * only 0 can be written, to clear the flag. tcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcsr0 is initialized to h'18 by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * tcsr is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. bit 7overflow flag (ovf): a status flag that indicates that tcnt has overflowed from h'ff to h'00. 419 bit 7 ovf description 0 [clearing condition] * read tcsr when ovf = 1, then write 0 in ovfa (initial value) 1 [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. note: * when the interval timer interrupt is disabled and ovf is polled, read the state of ovf = 1 twice or more. bit 6timer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. if wdt is used in watchdog timer mode, it can generate a reset when tcnt overflows. if wdt is used in interval timer mode, it generates a wovi interrupt request to the cpu when tcnt overflows. bit 6 wt/ it description 0 interval timer mode: interval timer interrupt (wovi) request is sent to cpu when tcnt overflows (initial value) 1 watchdog timer mode: internal reset can be selected when tcnt overflows * note: * for details of the case where tcnt overflows in watchdog timer mode, see section 11.2.3, reset control/status register (rstcsr). bit 5timer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and count operation is halted (initial value) 1 tcnt counts wdt0 tcsr bits 4 and 3reserved: these bits cannot be modified and are always read as 1. bits 2 to 0clock select 2 to 0 (cks2 to cks0): these bits select an internal clock source, obtained by dividing the system clock (?) for input to tcnt. 420 bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period * (when ? = 10 mhz) 0 0 0 ?/2 (initial value) 51.2 s 1 ?/64 1.6 ms 1 0 ?/128 3.2 ms 1 ?/512 13.2 ms 1 0 0 ?/2048 52.4 ms 1 ?/8192 209.8 ms 1 0 ?/32768 838.8 ms 1 ?/131072 3.36 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. 11.2.3 reset control/status register (rstcsr) 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 bit : initial value : r/w : note: * only 0 can be written, to clear the flag. rstcsr is an 8-bit readable/writable* register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the internal reset signal caused by a wdt overflow. note: * rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. 421 bit 7watchdog overflow flag (wovf): indicates that tcnt has overflowed (from h'ff to h'00) during watchdog timer operation. this bit is not set in interval timer mode. bit 7 wovf description 0 [clearing condition] (initial value) cleared by reading rstcsr when wovf = 1, then writing 0 to wovf 1 [setting condition] when tcnt overflows (from hff to h00) in watchdog timer mode bit 6reset enable (rste): specifies whether or not an internal reset signal is generated if tcnt overflows in watchdog timer mode. bit 6 rste description 0 no internal reset when tcnt overflows * (initial value) 1 internal reset is generated when tcnt overflows note: * the chip is not reset internally, but tcnt and tcsr in wdt0 are reset. bit 5reset select (rsts): selects the type of internal reset generated if tcnt overflows in watchdog timer mode. for details of the types of resets, see section 4, exception handling. bit 5 rsts description 0 power-on reset (initial value) 1 manual reset bits 4 to 0reserved: these bits cannot be modified and are always read as 1. 422 11.2.4 notes on register access the watchdog timers tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transfer instruction. they cannot be written to with byte transfer instructions. figure 11-2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ff74 address: h'ff74 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 11-2 format of data written to tcnt and tcsr (example of wdt0) writing to rstcsr: rstcsr must be written to by a word transfer to address h'ff76. it cannot be written to with byte instructions. figure 11-3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit differs from that for writing to the rste and rsts bits. to write 0 to the wovf bit, the upper byte of the written word must contain h'a5 and the lower byte must contain h'00. this clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the values in bits 6 and 5 of the lower byte into the rste and rsts bits, but has no effect on the wovf bit. 423 h'a5 h'00 15 8 7 0 h'5a write data 15 8 7 0 writing 0 to wovf bit writing to rste and rsts bits address: h'ffbe address: h'ffbe figure 11-3 format of data written to rstcsr (example of wdt0) reading tcnt, tcsr, and rstcsr: these registers are read in the same way as other registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr. 424 11.3 operation 11.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it and tme bits in tcsr to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally by writing h'00) before overflow occurs. this ensures that tcnt does not overflow while the system is operating normally. in this way, tcnt will not overflow while the system is operating normally, but if tcnt is not rewritten and overflows because of a system crash or other error, in the case of wdt, if the rste bit in rstcsr is set to 1 beforehand, a signal is generated that effects an internal chip reset. either a power-on reset or a manual reset can be selected with the rsts bit in rstcsr. the internal reset signal is output for 518 states. this is illustrated in figure 11-4. if a reset caused by an input signal from the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the wovf bit in rstcsr is cleared to 0. tcnt value h'00 time h'ff wt/it = 1 tme = 1 h'00 written to tcnt wt/it = 1 tme = 1 h'00 written to tcnt 518 states (wdt0) internal reset signal * overflow internal reset generated wovf = 1 wt/it: timer mode select bit tme: timer enable bit note: * with wdt, the internal reset signal is generated only when the rste bit is set to 1. figure 11-4 operation in watchdog timer mode 425 11.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 11-5. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interru p t re q uest g eneration wovi wovi wovi figure 11-5 operation in interval timer mode 426 11.3.3 timing of setting of overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure11-6. ? ?1 ?1 ?1 tcnt h'ff h'00 overflow signal (internal signal) ovf figure 11-6 timing of ovf setting 11.3.4 timing of setting of watchdog timer overflow flag (wovf) with wdt, the wovf bit in rstcsr is set to 1 if tcnt overflows in watchdog timer mode. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire chip. this timing is illustrated in figure 11-7. 427 ? tcnt h'ff h'00 overflow signal (internal signal) internal reset signal wovf 518 states (wdt) figure 11-7 timing of wovf setting 11.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. 428 11.5 usage notes 11.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 11-8 shows this operation. address ? internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 11-8 contention between tcnt write and increment 11.5.2 changing value of cks2 to cks0 if bits cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits cks2 to cks0. 11.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode. 429 11.5.4 internal reset in watchdog timer mode if the rste bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally if tcnt overflows, but tcnt and tcsr in wdt will be reset. tcnt, tcsr, and rstcr cannot be written to for a 132-state interval after overflow occurs, and a read of the wovf flag is not recognized during this time. it is therefore necessary to wait for 132 states after overflow occurs before writing 0 to the wovf flag to clear it. 430 431 section 12 serial communication interface (sci) 12.1 overview the h8s/2214 is equipped with mutually independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). sci0 allows a choice of 720 kbps, 460.784 kbps, or 115.192 kbps at 16 mhz operation. 12.1.1 features sci features are listed below. ? choice of asynchronous or clocked synchronous serial communication mode asynchronous mode ? serial data communication executed using asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length : 7 or 8 bits stop bit length : 1 or 2 bits parity: even, odd, or none multiprocessor bit : 1 or 0 ? receive error detection : parity, overrun, and framing errors ? break detection :break can be detected by reading the rxd pin level directly in case of a framing error ? average transfer rate generator (sci0): 720 kbps, 460.784 kbps, or 115.192 kbps can be selected at 16 mhz ? a transfer rate clock can be input from the tpu (sci0) clocked synchronous mode ? serial data communication synchronized with a clock 432 serial data communication can be carried out with other chips that have a synchronous communication function ? one serial data transfer format data length : 8 bits ? receive error detection : overrun errors detected ? sci select function (sci0: txd0 = high-impedance and sck0 = fixed high-level input can be selected when irq7 = 1) ? full-duplex communication capability ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data ? choice of lsb-first or msb-first transfer ? can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) note: * descriptions in this section refer to lsb-first transfer. ? on-chip baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources ? four interrupt sources transmit-data-empty, transmit-end, receive-data-full, and receive error that can issue requests independently ? the transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (dtc) or dma controller (dmac) to execute data transfer ? module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode. 433 12.1.2 block diagram figures 12-1 and 12-2 show block diagrams of the sci. parity generation parity check transmit/ receive control baud rate generator clock external clock average transfer rate generator at 10.667 mhz ? 115.152 kbps ? 460.606 kbps at 16 mhz ? 115.192 kbps ? 460.784 kbps ? 720 kbps bus interface internal data bus rxd0 rdr tdr rsr tsr scmr ssr scr smr semr brr /4 /16 /64 tei txi rxi eri sck0 c/ a cke1 sse rsr rdr tsr tdr smr legend: receive shift register receive data register transmit shift register transmit data register serial mode register scr ssr scmr brr semr serial control register serial status register serial card mode register bit rate register serial extended mode register : : : : : : : : : : txd0 pg1/ irq7 sci0 module data bus tpu tioca1 tioca2 tclka figure 12-1 block diagram of sci0 434 bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock ? ?/4 ?/16 ?/64 txi tei rxi eri smr legend rsr rdr tsr tdr smr scr ssr scmr brr : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register :smart card mode register : bit rate register figure 12-2 block diagram of sci1 and sci2 435 12.1.3pin configuration table 12-1 shows the serial pins for each sci channel. table 12-1 sci pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output note: pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. 436 12.1.4 register configuration the sci has the internal registers shown in table 12-2. these registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. table 12-2 sci registers channel name abbreviation r/w initial value address* 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w)* 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e serial expansion mode register 0 semr0 r/w h'00 h'fdf8 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w)* 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w)* 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e all module stop control register b mstpcrb r/w h'ff h'fde9 notes: *1 lower 16 bits of the address. *2 can only be written with 0 for flag clearing. 437 12.2 register descriptions 12.2.1 receive shift register (rsr) 7 6 5 4 3 0 2 1 bit r/w : : rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 12.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 438 12.2.3 transmit shift register (tsr) 7 6 5 4 3 0 2 1 bit r/w : : tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 12.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 439 12.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : smr is an 8-bit register used to set the scis serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bit 7communication mode (c/ a ): selects asynchronous mode or clocked synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6character length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in clocked synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer. 440 bit 5parity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4parity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e description 0 even parity* 1 (initial value) 1 odd parity* 2 notes: *1 when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. *2 when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 441 bit 3stop bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bits setting is only valid in asynchronous mode. if clocked synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (initial value) 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2multiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. for details of the multiprocessor communication function, see section 12.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected bits 1 and 0clock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from ?, ?/4, ?/16, and ?/64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 12.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 0 0 ? clock (initial value) 1 ?/4 clock 1 0 ?/16 clock 1 ?/64 clock 442 12.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bit 7transmit interrupt enable (tie): enables or disables transmit data empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit data empty interrupt (txi) requests disabled * (initial value) 1 transmit data empty interrupt (txi) requests enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0. bit 6receive interrupt enable (rie): enables or disables receive data full interrupt (rxi) request and receive error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled * (initial value) 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. 443 bit 5transmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled* 1 (initial value) 1 transmission enabled* 2 notes: *1 the tdre flag in ssr is fixed at 1. *2 in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. bit 4receive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled* 1 (initial value) 1 reception enabled* 2 notes: *1 clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. *2 serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1. 444 bit 3multiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in smr is set to 1. the mpie bit setting is invalid in clocked synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2transmit end interrupt enable (teie): enables or disables transmit end interrupt (tei) request generation when there is no valid transmit data in tdr in msb data transmission. bit 2 teie description 0 transmit end interrupt (tei) request disabled * (initial value) 1 transmit end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0. bits 1 and 0clock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (cke1 = 1). note that the scis operating mode must be decided using smr after setting the cke1 and cke0 bits. 445 for details of clock source selection, see table 12.9 in section 12.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port* 1 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 asynchronous mode internal clock/sck pin functions as clock output* 2 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input* 3 clocked synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input* 3 clocked synchronous mode external clock/sck pin functions as serial clock input notes: *1 initial value *2 outputs a clock of the same frequency as the bit rate. *3 inputs a clock with a frequency 16 times the bit rate. 12.2.7 serial status register (ssr) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : note: * only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. 446 bit 7transmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr bit 6receive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5overrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value)* 1 when 0 is written to orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1* 2 notes: *1 the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. *2 the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 447 bit 4framing error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value)* 1 when 0 is written to fer after reading fer = 1 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: *1 the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. *2 in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 3parity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value)* 1 when 0 is written to per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr* 2 notes: *1 the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. *2 if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. 448 bit 2transmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1multiprocessor bit (mpb): when reception is performed using multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0multiprocessor bit transfer (mpbt): when transmission is performed using multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted 449 12.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 12-3 shows sample brr settings in asynchronous mode, and table 12-4 shows sample brr settings in clocked synchronous mode. 450 table 12-3brr settings for various bit rates (asynchronous mode) ? = 2 mhz ? = 2.097152 mhz ? = 2.4576 mhz ? = 3 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 C0.04 1 174 C0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 C0.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 C2.48 0 15 0.00 0 19 C2.34 9600 0 6 C2.480 7 0.000 9 C2.34 19200 0 3 0.000 4 C2.34 31250 0 1 0.00 0 2 0.00 38400 0 1 0.00 ? = 3.6864 mhz ? = 4 mhz ? = 4.9152 mhz ? = 5 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 C0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 C1.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.000 7 1.73 31250 0 3 0.000 4 C1.700 4 0.00 38400 0 2 0.00 0 3 0.000 3 1.73 451 ? = 6 mhz ? = 6.144 mhz ? = 7.3728 mhz ? = 8 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 C0.44 2 108 0.08 2 130 C0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 C2.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 C2.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 C2.34 0 4 0.00 0 5 0.00 ? = 9.8304 mhz ? = 10 mhz ? = 12 mhz ? = 12.288 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 C0.26 2 177 C0.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 C1.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 C2.34 0 19 0.00 31250 0 9 C1.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 C2.34 0 9 0.00 452 ? = 14 mhz ? = 14.7456 mhz ? = 16 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) 110 2 248 C0.17 3 64 0.70 3 70 0.03 150 2 181 0.13 2 191 0.00 2 207 0.16 300 2 90 0.13 2 95 0.00 2 103 0.16 600 1 181 0.13 1 191 0.00 1 207 0.16 1200 1 90 0.13 1 95 0.00 1 103 0.16 2400 0 181 0.13 0 191 0.00 0 207 0.16 4800 0 90 0.13 0 95 0.00 0 103 0.16 9600 0 45 C0.93 0 47 0.00 0 51 0.16 19200 0 22 C0.93 0 23 0.00 0 25 0.16 31250 0 13 0.00 0 14 C1.70 0 15 0.00 38400 0 110.000 120.16 453 table 12-4 brr settings for various bit rates (clocked synchronous mode) bit rate ? = 2 mhz ? = 4 mhz ? = 6 mhz ? = 8 mhz ? = 10 mhz ? = 16 mhz (bit/s) nnnnnnnnnnnn 110 3 70 250 2 124 2 249 3 124 3 249 500 1 249 2 124 2 249 3 124 1 k 1 124 1 249 2 124 2 249 2.5 k 0 199 1 99 1 149 1 199 1 249 2 99 5 k 0 99 0 199 1 74 1 99 1 124 1 199 10 k 0 49 0 99 0 149 0 199 0 249 1 99 25 k 0 19 0 39 0 59 0 79 0 99 0 159 50 k 09019029039049079 100 k 0409014019024039 250 k 0103050709015 500 k 0 0 * 0102030407 1 m 0 0 * 01 03 2.5 m 00 * 5 m note: as far as possible, the setting should be made so that the error is no more than 1%. legend blank : cannot be set. : can be set, but there will be a degree of error. * : continuous transfer is not possible. 454 the brr setting is found from the following formulas. asynchronous mode: n = ? 64 2 2nC1 b 10 6 C 1 clocked synchronous mode: n = ? 8 2 2nC1 b 10 6 C 1 where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) ?: operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0? 0 0 1 ?/4 0 1 2 ?/16 1 0 3 ?/64 1 1 the bit rate error in asynchronous mode is found from the following formula: error (%) = { ? 10 6 (n + 1) b 64 2 2nC1 C 1 } 100 455 table 12-5 shows the maximum bit rate for each frequency in asynchronous mode. tables 12-6 and 12-7 show the maximum bit rates with external clock input. when the abcs bit in sci0's serial expansion mode register 0 (semr0) is set to 1 in asynchronous mode, the maximum bit rates are twice those shown in tables 12-5 and 12-6. table 12-5 maximum bit rate for each frequency (asynchronous mode) ? (mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0 14 437500 0 0 14.7456 460800 0 0 16 500000 0 0 456 table 12-6 maximum bit rate with external clock input (asynchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 14 3.5000 218750 14.7456 3.6864 230400 16 4.0000 250000 table 12-7 maximum bit rate with external clock input (clocked synchronous mode) ? (mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 457 12.2.9 smart card mode register (scmr) 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : scmr selects lsb-first or msb-first by means of bit sdir. except in the case of asynchronous mode 7-bit data, lsb-first or msb-first can be selected regardless of the serial communication mode scmr is initialized to h'f2 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bits 7 to 4reserved: read-only bits, always read as 1. bit 3smart card data transfer direction (sdir): selects the serial/parallel conversion format. this bit is valid when 8-bit data is used as the transmit/receive format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first 458 bit 2smart card data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr. bit 2 sinvdescription 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1reserved: read-only bit, always read as 1. bit 0reserved: this bit can be read or written to, but only 0 should be written. 12.2.10 serial extended mode register 0 (semr0) 7 sse 0 r/w 6 undefined 5 undefined 4 undefined 3 abcs 0 r/w 0 acs0 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w bit initial value r/w : : : semr0 is an 8-bit register that extends the functions of sci0. semr0 enables selection of the sci0 select function in synchronous mode, base clock setting in asynchronous mode, and also clock source selection and automatic transfer rate setting. semr0 is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode and software standby mode. 459 bit 7sci0 select enable (sse): allows selection of the sci0 select function when an external clock is input in synchronous mode. when the sci0 select function is enabled, if 1 is input to the pg1/irq7 pin, txd0 output goes to the high-impedance state, sck0 input is fixed high inside the chip, and sci0 data transmission/reception is halted. the sse setting is valid when external clock input is used (cke1 = 1 in scr) in synchronous mode (c/ a = 1 in smr). when an internal clock is selected (cke1 = 0 in scr) in synchronous mode, or when the chip is in asynchronous mode (c/ a = 0 in smr), the sci0 select function is disabled even if sse is set to 1. bit 7 sse description 0 sci0 select function disabled (initial value) 1 sci0 select function enabled when pg1/irq7 pin input = 1, txd0 output goes to high-impedance state and sck0 clock input is fixed high bits 6 to 4reserved: write 0 to these bits. bit 3asynchronous base clock select (abcs): selects the 1-bit-interval base clock in asynchronous mode. the abcs setting is valid in asynchronous mode (c/ a = 0 in smr). it is invalid in synchronous mode (c/ a = 1 in smr). bit 3 abcs description 0 sci0 operates on base clock with frequency of 16 times transfer rate (initial value) 1 sci0 operates on base clock with frequency of 8 times transfer rate 460 bits 2 to 0asynchronous clock source select 2 to 0 (acs2 to acs0): these bits select the clock source in asynchronous mode. when an average transfer rate is selected, the base clock is set automatically regardless of the abcs value. note that average transfer rates are not supported for operating frequencies other than 10.667 mhz and 16 mhz. the setting in bits acs2 to acs0 is valid when external clock input is used (cke1 = 1 in scr) in asynchronous mode (c/ a = 0 in smr). the setting in acs2 to acs0 is invalid when an internal clock is selected (cke1 = 0 in scr) in asynchronous mode, or when the chip is in synchronous mode (c/ a = 1 in smr). bit 2 bit 1 bit 0 acs2 acs1 acs0 description 0 0 0 external clock input (initial value) 1 115.152 kbps average transfer rate (for ? = 10.667 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 1 0 460.606 kbps average transfer rate (for ? = 10.667 mhz only) is selected (sci0 operates on base clock with frequency of 8 times transfer rate) 1 reserved 1 0 0 tpu clock input (and of tioca1 and tioca2) 1 115.196 kbps average transfer rate (for ? = 16 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 1 0 460.784 kbps average transfer rate (for ? = 16 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 1 720 kbps average transfer rate (for ? = 16 mhz only) is selected (sci0 operates on base clock with frequency of 8 times transfer rate) 461 figures 12-3 and 12-4 show examples of the internal base clock when an average transfer rate is selected. 1234567891011 12345678 12 13 14 15 16 17 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 5.333 mhz 3.6848 mhz 1 bit = base clock 8 * base clock 10.667 mhz/2 = 5.333 mhz 5.333 mhz (38/55) = 3.6848 mhz (average) 123 123 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 23 22 4 5 6 7 8 9 10 11 12 13 14 15 16 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 28 29 2.667 mhz 1.8424 mhz 1 bit = base clock 16 * base clock 10.6677 mhz/4= 2.667 mhz 2.667 mhz (38/55) = 1.8424 mhz (average) when ? = 10.667 mhz base clock with 460.606 kbps average transfer rate base clock with 115.152 kbps average transfer rate average transfer rate = 1.8424 mhz/16= 115.152 kbps average error = -0.043% average transfer rate = 3.6848 mhz/8= 460.606 kbps average error = -0.043% note: * as the base clock synchronization varies, so does the length of one bit. figure 12-3 examples of base clock when average transfer rate is selected (1) 462 12345678910 123 45 678 11 12 13 14 15 16 17 18 19 20 21 23 22 2425 1 2 5 6 7 8 9 101112131415 161718 19202122232425 34 8 mhz base clock 16 mhz/2 = 8 mhz 8 mhz (47/51)= 7.3725 mhz (average) 7.3725 mhz 1 bit = base clock 16 * 1234567891011121314151617 123456789101112 13141516 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 28 29 8 mhz base clock 16 mhz/2 = 8 mhz 8 mhz (18/25)= 5.76 mhz (average) base clock with 460.784 kbps average transfer rate average transfer rate = 7.3725 mhz/16= 460.784 kbps average error = -0.004% average transfer rate = 5.76 mhz/8= 720 kbps average error = 0% base clock with 720 kbps average transfer rate 5.76 mhz 1 bit = base clock 8 * 123 2 mhz 1.8431 mhz 1 bit = base clock 16 * base clock 16 mhz/8 = 2 mhz 2 mhz (47/51)= 1.8431 mhz (average) 4567891011121314151617 123456789101112 13141516 18 19 20 21 23 22 24 25 26 27 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 28 29 when ? = 16 mhz base clock with 115.196 kbps average transfer rate average transfer rate = 1.8431 mhz/16= 115.196 kbps average error = -0.004% note: * as the base clock synchronization varies, so does the length of one bit. figure 12-4 examples of base clock when average transfer rate is selected (2) 463 12.2.11 module stop control register b (mstpcrb) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w : : : mstpcrb is an 8-bit readable/writable register that performs module stop mode control. when one of bits mstpb7 to mstpb5 is set to 1, sci0, sci1, or sci2 respectively, stops operation at the end of the bus cycle, and enters module stop mode. for details, see section 17.5, module stop mode. mstpcrb is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7module stop (mstpb7): specifies the sci0 module stop mode. bit 7 mstpb7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value) bit 6module stop (mstpb6): specifies the sci1 module stop mode. bit 6 mstpb6 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) bit 5module stop (mstpb5): specifies the sci2 module stop mode. bit 5 mstpb5 description 0 sci2 module stop mode is cleared 1 sci2 module stop mode is set (initial value) 464 12.3operation 12.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or clocked synchronous mode and the transmission format is made using smr as shown in table 12-8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 12-9. asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overrun errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) clocked synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock 465 table 12-8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 data parity stop bit c/ a chr mp pe stop mode length bit length 00000 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 8-bit data yes no 1 bit 1 2 bits 1 0 7-bit data 1 bit 1 2 bits 1 cl ocked synchronous mode 8-bit data no none table 12-9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 bit 1 bit 0 clock c/ a cke1 cke0 mode source sck pin function 0 0 0 asynchronous internal sci does not use sck pin 1 mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times 1 the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 multi processor bit asynchronous mode (multi- processor format) clocked synchronous mode 466 table 12-10 smr0, scr0, semr0 settings and sci clock source selection (sci0 only) smr0 scr0 setting semr0 setting sci transmit/receive clock bit 7 bit 1 bit 0 bit 2 bit 1 bit 0 clock c/ a cke1 cke0 acs2 acs1 acs0 mode source sck pin function 000 *** asynchronous mode internal sci does not use sck pin 1 outputs clock with some frequency as bit rate 1 * 0 0 0 external inputs clock with frequency of 16 or 8 times the bit rate 1 average transfer rate generator (115.152 kbps at 10.667 mhz) sci does not use sck pin 1 0 average transfer rate generator (460.606 kbps at 10.667 mhz) sci does not use sck pin 1 1 0 0 tpu (and of t10ca1 and t10ca2) sci does not use sck pin 1 average transfer rate generator (115.196 kbps at 16 mhz) sci does not use sck pin 1 0 average transfer rate generator (460.784 kbps at 16 mhz) sci does not use sck pin 1 average transfer rate generator (720 kbps at 16 mhz) sci does not use sck pin 467 smr0 scr0 setting semr0 setting sci transmit/receive clock bit 7 bit 1 bit 0 bit 2 bit 1 bit 0 clock c/ a cke1 cke0 acs2 acs1 acs0 mode source sck pin function 10 1 0 1 0 *** clocked synchronous mode internal external outputs serial clock input serial clock 1 12.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 12-5 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. when the abcs bit in semr0 is set to 1, sci0 samples the data on the 4th pulse of a clock with a frequency of 8 times the length of one bit. 468 lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 12-5 data format in asynchronous communication (example with 8-bit data, parity, two stop bits) 469 data transfer format: table 12-11 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. table 12-11 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend s : start bit stop : stop bit p : parity bit mpb : multiprocessor bit 470 clock: either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the scis serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 12-9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 12-6. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 12-6 relation between output clock and transfer data phase (asynchronous mode) data transfer operations: ? sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 471 figure 12-7 shows a sample sci initialization flowchart. wait 472 ? serial data transmission (asynchronous mode) figure 12-8 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no 473 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. 474 figure 12-9 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 12-9 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit) 475 ? serial data reception (asynchronous mode) figures 12-10 and 12-11 show a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes 476 477 in serial reception, the sci operates as described below. [1] the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] the received data is stored in rsr in lsb-to-msb order. [3] the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. [a] parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. [b] stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. [c] status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error* is detected in the error check, the operation is as shown in table 12-11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive error interrupt (eri) request is generated. 478 table 12-12 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr. framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr. parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr. figure 12-12 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine figure 12-12 example of sci operation in reception (example with 8-bit data, parity, one stop bit) 479 12.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station , and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 12-13 shows an example of inter-processor communication using the multiprocessor format. data transfer format: there are four data transfer formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 12-11. clock: see the section on asynchronous mode. 480 transmitting station receiving station a (id= 01) receiving station b (id= 02) receiving station c (id= 03) receiving station d (id= 04) serial transmission line serial data id transmission cycle= receiving station specification data transmission cycle= data transmission to receiving station specified by id (mpb= 1) (mpb= 0) h'01 h'aa legend mpb: multiprocessor bit figure 12-13 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer operations: ? multiprocessor serial data transmission figure 12-14 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission. 481 no 482 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] multiprocessor bit one multiprocessor bit (mpbt value) is output. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmission end interrupt (tei) request is generated. 483 figure 12-15 shows an example of sci operation for transmission using the multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 12-15 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) ? multiprocessor serial data reception figures 12-16 and 12-17 show a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception. 484 yes 485 486 figure 12-18 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this stations id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match stations id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this stations id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches stations id data2 id1 figure 12-18 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit) 487 12.3.4 operation in clocked synchronous mode in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 12-19 shows the general format for clocked synchronous serial communication. dont care dont care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 12-19 data format in synchronous communication in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in clocked serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in clocked synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 12-9. when the sci is operated on an internal clock, the serial clock is output from the sck pin. 488 eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. if you want to perform receive operations in units of one character, you should select an external clock as the clock source. data transfer operations: ? sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 12-20 shows a sample sci initialization flowchart. wait 489 ? serial data transmission (clocked synchronous mode) figure 12-21 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no 490 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). [3] the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. [4] after completion of serial transmission, the sck pin is fixed. figure 12-22 shows an example of sci operation in transmission. transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 12-22 example of sci operation in transmission 491 ? serial data reception (clocked synchronous mode) figure 12-23 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to clocked synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible. 492 yes 493 in serial reception, the sci operates as described below. [1] the sci performs internal initialization in synchronization with serial clock input or output. [2] the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 12-11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive error interrupt (eri) request is generated. figure 12-24 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated eri interrupt request generated by overrun error figure 12-24 example of sci operation in reception ? simultaneous serial data transmission and reception (clocked synchronous mode) figure 12-25 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations. 494 yes 495 12.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 12-13 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in the scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dmac or dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dmac or dtc. the dmac or dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dmac or dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dmac or dtc. the dmac or dtc cannot be activated by an eri interrupt request. 496 table 12-13sci interrupt sources channel interrupt source description dmac activation dtc activation priority * 0 eri interrupt due to receive error (orer, fer, or per) not possible not possible high rxi interrupt due to receive data full state (rdrf) possible possible txi interrupt due to transmit data empty state (tdre) possible possible tei interrupt due to transmission end (tend) not possible not possible 1 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible possible txi interrupt due to transmit data empty state (tdre) possible possible tei interrupt due to transmission end (tend) not possible not possible 2 eri interrupt due to receive error (orer, fer, or per) not possible not possible rxi interrupt due to receive data full state (rdrf) possible not possible txi interrupt due to transmit data empty state (tdre) possible not possible tei interrupt due to transmission end (tend) not possible not possible low note: * this table shows the initial state immediately after a reset. relative priorities among channels can be changed by means of the interrupt controller. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt may have priority for acceptance, with the result that the tdre and tend flags are cleared. note that the tei interrupt will not be accepted in this case. 497 12.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 12-14. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 12-14 state of ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr to rdr receive error status 1100x overrun error 0010 framing error 0001 parity error 1110x overrun error + framing error 1101x overrun error + parity error 0011 framing error + parity error 1111x overrun error + framing error + parity error notes: : receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr. 498 break detection and processing (asynchronous mode only): when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. sending a break (asynchronous mode only): the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin are first set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (clocked synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 12-26. 499 internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 12-26 receive data sampling timing in asynchronous mode thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 C 1 2n ) C (l C 0.5) f C | d C 0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 C 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 500 restrictions on use of dmac or dtc ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ? clock cycles after tdr is updated by the dmac or dtc. misoperation may occur if the transmit clock is input within 4 ? clocks after tdr is updated. (figure 12-27) ? when rdr is read by the dmac or dtc, be sure to set the activation source to the relevant sci reception end interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t >4 clocks. tdre figure 12-27 example of clocked synchronous transmission by dtc operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, software standby mode, or subsleep mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode, software standby mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted will be undefined. when transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read -> tdr write -> tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 12- 28 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 12-29 and 12-30. operation should also be stopped (by clearing te, tie, and teie to 0) before making a transition from transmission by dtc transfer to module stop mode, software standby mode, or subsleep mode transition. to perform transmission with the dtc after the relevant mode is cleared, setting te and tie to 1 will set the txi flag and start dtc transmission. 501 ? reception ? receive operation should be stopped (by clearing re to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. rsr, rdr, and ssr are reset. if a transition is made without stopping operation, the data being received will be invalid. ? to continue receiving without changing the reception mode after the relevant mode is cleared, set re to 1 before starting reception. to receive with a different receive mode, the procedure must be started again from initialization. ? figure 12-31 shows a sample flowchart for mode transition during reception. read tend flag in ssr te= 0 transition to software standby mode, etc. exit from software standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes 502 sck output pin te bit txd output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to software standby exit from software standby figure 12-29 asynchronous transmission using internal clock port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized by software standby. sck output pin te bit txd output pin sci txd output start of transmission end of transmission transition to software standby exit from software standby figure 12-30 synchronous transmission using internal clock 503 re= 0 transition to software standby mode, etc. read receive data in rdr read rdrf flag in ssr exit from software standby mode, etc. change operating mode? no rdrf= 1 yes yes 504 switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 12-32) sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3. c/a= 0 2.te = 0 half-cycle low-level output figure 12-32 operation when switching from sck pin function to port pin function 505 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/port pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 3.cke1= 1 5.cke1= 0 4. c/a= 0 2.te = 0 high-level outputte figure 12-33 operation when switching from sck pin function to port pin function (example of preventing low-level output) 506 507 section 13 d/a converter 13.1 overview the h8s/2214 includes a one-channel d/a converter. 13.1.1 features d/a converter features are listed below ? 8-bit resolution ? one output channel ? maximum conversion time of 10 s (with 20 pf load) ? output voltage of 0 v to vref ? d/a output hold function in software standby mode ? module stop mode can be set ? as the initial setting, d/a converter operation is halted. register access is enabled by exiting module stop mode. 508 13.1.2 block diagram figure 13-1 shows a block diagram of the d/a converter. module data bus internal data bus vref avcc da0 avss 8-bit d/a control circuit dadr0 bus interface dacr figure 13-1 block diagram of d/a converter 509 13.1.3 pin configuration table 13-1 summarizes the input and output pins of the d/a converter. table 13-1 pin configuration pin name symbol i/o function analog power pin avcc input analog power source analog ground pin avss input analog ground and reference voltage analog output pin 0 da0 output channel 0 analog output reference voltage pin vref input analog reference voltage 13.1.4 register configuration table 13-2 summarizes the registers of the d/a converter. table 13-2 d/a converter registers name abbreviation r/w initial value address * d/a data register 0 dadr0 r/w h'00 h'fdac d/a control register dacr r/w h'1f h'fdae module stop control register c mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address. 13.2 register descriptions 13.2.1 d/a data register 0 (dadr0) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : d/a data register 0 (dadr0) is an 8-bit readable/writable registers that stores data for conversion. whenever output is enabled, the value in the d/a data register is converted and output from the analog output pin. dadr0 is initialized to h'00 by a reset and in hardware standby mode. 510 13.2.2 d/a control register (dacr) 7 0 r/w 6 daoe0 0 r/w 5 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in hardware standby mode. bit 7reserved: only 0 should be written to this bit. bit 6d/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 analog output da0 is disabled (initial value) 1 channel 0 d/a conversion is enabled; analog output da0 is enabled bit 5reserved: only 0 should be written to this bit. if the h8s/2214 enters software standby mode when d/a conversion is enabled, the d/a output is held and the analog power current is the same as during d/a conversion. when it is necessary to reduce the analog power current in software standby mode, clear the daoe0 bit to 0 to disable d/a output. bits 4 to 0reserved: read-only bits, always read as 1. 13.2.3 module stop control register c (mstpcrc) 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 * r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w : : : mstpcrc is an 8-bit readable/writable register that performs module stop mode control. when the mstpc5 bit in mstpcr is set to 1, d/a converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 17.5, module stop mode. 511 mstpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 5module stop (mstpc5): specifies the d/a converter module stop mode. bit 5 mstpc5 description 0 d/a converter module stop mode cleared 1 d/a converter module stop mode set (initial value) 13.3 operation d/a conversion is performed continuously while enabled by dacr. if either dadr0 is written to, the new data is immediately converted. the conversion result is output by setting the corresponding daoe0 bit to 1. the operation example described in this section concerns d/a conversion on channel 0. figure 13-2 shows the timing of this operation. [1] write the conversion data to dadr0. [2] set the daoe0 bit in dacr to 1. d/a conversion is started and the da0 pin becomes an output pin. the conversion result is output after the conversion time has elapsed. the output value is expressed by the following formula: dadr contents 256 vref the conversion results are output continuously until dadr0 is written to again or the daoe0 bit is cleared to 0. [3] if dadr0 is written to again, the new data is immediately converted. the new conversion result is output after the conversion time has elapsed. [4] if the daoe0 bit is cleared to 0, the da0 pin becomes an input pin. 512 conversion data 1 conversion result 1 high-impedance state t dconv dadr0 write cycle da0 daoe0 dadr0 address ? dacr write cycle conversion data 2 conversion result 2 t dconv legend t dconv : d/a conversion time dadr0 write cycle dacr write cycle figure 13-2 example of d/a converter operation 513 section 14 ram 14.1 overview the h8s/2214 has 12 kbytes of on-chip high-speed static ram. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 14.1.1 block diagram figure 14-1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffc000 h'ffc002 h'ffc004 h'ffffc0 h'ffc001 h'ffc003 h'ffc005 h'ffffc1 h'fffffe h'ffffff h'ffefbe h'ffefbf figure 14-1 block diagram of ram 514 14.1.2 register configuration the on-chip ram is controlled by syscr. table 14-1 shows the address and initial value of syscr. table 14-1 ram register name abbreviation r/w initial value address * system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address. 14.2 register descriptions 14.2.1 system control register (syscr) 7 0 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0ram enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) 515 14.3 operation when the rame bit is set to 1, accesses to addresses h'ffc000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2214 is directed to the on-chip ram. when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written to and read in byte or word units. each type of access can be performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 14.4 usage note dtc register information can be located in addresses h'ffebc0 to h'ffefbf. when the dtc is used, the rame bit must not be cleared to 0. 516 517 section 15 rom 15.1 overview the h8s/2214 has 128 kbytes of on-chip rom (flash memory or mask rom). the rom is connected to the cpu by a 16-bit data bus. the cpu accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. the on-chip rom is enabled or disabled by setting the mode pins (md2, md1, and md0). the flash memory versions can be erased and programmed on-board as well as with a prom programmer. 15.1.1 block diagram figure 15-1 shows a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'000001 h'000003 h'01fffe h'01ffff figure 15-1 block diagram of rom 518 15.1.2 register configuration the h8s/2214s on-chip rom is controlled by the mode pins. the register configuration is shown in table 15-1. table 15-1 rom register name abbreviation r/w initial value address * mode control register mdcr r/w undefined h'fde7 note: * lower 16 bits of the address. 15.2 register descriptions 15.2.1 mode control register (mdcr) bit:7 65 43 21 0 mds2 mds1 mds0 initial value : 1 0 0 0 0 * * * r/w: r r r note: * determined by pins md2 to md0. mdcr is an 8-bit read-only register that indicates the current operating mode of the h8s/2214. bit 7reserved: read-only bit, always read as 1. bits 6 to 3reserved: read-only bits, always read as 0. bits 2 to 0mode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to pins md2 to md0. mds2 to mds0 are read-only bits, and cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a power-on reset, but are retained after a manual reset. 519 15.3 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the on-chip rom is enabled and disabled by setting the mode pins (md2, md1, and md0). these settings are shown in table 15-2. table 15-2 operating modes and rom area (f-ztat version and mask rom version) mode pin operating mode fwe md2 md1md0 on-chip rom mode 0 0000 mode 1 1 mode 2 1 0 mode 3 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (128 kbytes)* 1 mode 7 advanced single-chip mode 1 enabled (128 kbytes)* 1 mode 8 1000 mode 9 1 mode 10 boot mode (advanced expanded mode with on-chip rom enabled)* 1 1 0 enabled (128 kbytes)* 2 mode 11 boot mode (advanced single-chip mode)* 2 1 enabled (128 kbytes)* 2 mode 12 100 mode 13 1 mode 14 user program mode (advanced expanded mode with on-chip rom enabled)* 1 1 0 enabled (128 kbytes)* 1 mode 15 user program mode (advanced single- chip mode)* 2 1 enabled (128 kbytes)* 1 notes: *1 apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip rom enabled. *2 apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. 520 15.4 overview of flash memory 15.4.1 features the h8s/2214 has 128 kbytes of on-chip flash memory. the features of the flash memory are summarized below. ? four flash memory operating modes ? program mode ? erase mode ? program-verify mode ? erase-verify mode ? programming/erase methods the flash memory is programmed 128 bytes at a time. block erase (in single-block units) can be performed. to erase multiple blocks, each block must be erased in turn. in block erasing, 1- kbyte, 8-kbyte, 16-kbyte, 28-kbyte, and 32-kbyte block units can be set as required. ? programming/erase times the flash memory programming time is t.b.d ms (typ.) for simultaneous 128-byte programming, equivalent to t.b.d s (typ.) per byte, and the erase time is t.b.d ms (typ.). ? reprogramming capability the flash memory can be reprogrammed up to 100 times. ? on-board programming modes there are two modes in which flash memory can be programmed/erased/verified on-board: ? boot mode ? user program mode ? automatic bit rate adjustment with data transfer in boot mode, the lsis bit rate can be automatically adjusted to match the transfer bit rate of the host. ? flash memory emulation in ram flash memory programming can be emulated in real time by overlapping a part of ram onto flash memory. ? protect modes there are two protect modes, hardware and software, which allow protected status to be designated for flash memory program/erase/verify operations. ? programmer mode flash memory can be programmed/erased in programmer mode, using a prom programmer, as well as in on-board programming mode. 521 15.4.2 block diagram module bus bus interface/controller flash memory (128 kb) operating mode flmcr2 internal address bus internal data bus (16 bits) fwe pin mode pin ebr1 ebr2 ramer flmcr1 flash memory control register 1 flash memory control register 2 erase block register 1 erase block register 2 ram emulation register legend flmcr1: flmcr2: ebr1: ebr2: ramer: note: these registers are for use exclusively by the flash memory version. reads to the corresponding addresses in the mask rom version will return an undefined value, and writes to these addresses are invalid. figure 15-2 block diagram of flash memory 522 15.4.3 mode transitions when the mode pins and the fwe pin are set in the reset state and a reset-start is executed, the microcomputer enters an operating mode as shown in figure 15-3. transitions between user mode and user program mode should only be made when the cpu is not accessing the flash memory. the boot, user program and programmer modes are provided as modes to write and erase the flash memory. boot mode on-board programming mode user program mode user mode (on-chip rom enabled) reset state programmer mode res = 0 fwe = 1 fwe = 0 *1 *1 *2 notes: only make a transition between user mode and user program mode when the cpu is , ' , 334- *1 ram emulation possible *2 md0 = 0, md1 = 0, md2 = 0, p14 = 0, p16 = 0, pf0 = 1, pe3 = 1 res = 0 md1 = 1, md2 = 0, fwe = 1 res = 0 res = 0 md1 = 1, md2 = 1, fwe = 0 md1 = 1, md2 = 1, fwe = 1 figure 15-3 flash memory state transitions 523 15.4.4 on-board programming modes boot mode flash memory h8s/2214 ram host programming control program sci application program (old version) new application program flash memory h8s/2214 ram host sci application program (old version) boot program area new application program flash memory h8s/2214 ram host sci flash memory preprogramming erase boot program new application program flash memory h8s/2214 program execution state ram host sci new application program boot program programming control program 1. initial state the old program version or data remains written in the flash memory. the user should prepare the programming control program and new application program beforehand in the host. 2. programming control program transfer when boot mode is entered, the boot program in the h8s/2214 (originally incorporated in the chip) is started and the programming control program in the host is transferred to ram via sci communication. the boot program required for flash memory erasing is automatically transferred to the ram boot program area. 3. flash memory initialization the erase program in the boot program area (in ram) is executed, and the flash memory is initialized (to h'ff). in boot mode, total flash memory erasure is performed, without regard to blocks. 4. writing new application program the programming control program transferred from the host to ram is executed, and the new application program in the host is written into the flash memory. programming control program boot program boot program boot program area boot program area programming control program figure 15-4 boot mode 524 user program mode flash memory h8s/2214 ram host programming/ erase control program sci boot program new application program flash memory h8s/2214 ram host sci new application program flash memory h8s/2214 ram host sci flash memory erase boot program new application program flash memory h8s/2214 program execution state ram host sci boot program . 3 % 3 program application program (old version) ( program - the fwe assessment program that confirms that user program mode has been entered, and the program that will transfer the programming/erase control program from flash memory to on-chip ram should be written into the flash memory by the user beforehand. the programming/erase control program should be prepared in the host or in the flash memory. 2. programming/erase control program transfer when user program mode is entered, user software confirms this fact, executes transfer program in the flash memory, and transfers the programming/erase control program to ram. 3. flash memory initialization the programming/erase program in ram is executed, and the flash memory is initialized (to h'ff). erasing can be performed in block units, but not in byte units. 4. writing new application program next, the new application program in the host is written into the erased flash memory blocks. do not write to unerased blocks. programming/ erase control program programming/ erase control program programming/ erase control program transfer program application program (old version) transfer program fwe assessment program fwe assessment program transfer program fwe assessment program transfer program figure 15-5 user program mode 525 15.4.5 flash memory emulation in ram emulation should be performed in user mode or user program mode. when the emulation block set in ramer is accessed while the emulation function is being executed, data written in the overlap ram is read. application program execution state flash memory emulation block ram sci overlap ram (emulation is performed on data written in ram) figure 15-6 reading overlap ram data in user mode or user program mode when overlap ram data is confirmed, the rams bit is cleared, ram overlap is released, and writes should actually be performed to the flash memory. when the programming control program is transferred to ram, ensure that the transfer destination and the overlap ram do not overlap, as this will cause data in the overlap ram to be rewritten. 526 application program flash memory ram sci programming control program execution state overlap ram (programming data) programming data figure 15-7 writing overlap ram data in user program mode 15.4.6 differences between boot mode and user program mode table 15-3 differences between boot mode and user program mode boot mode user program mode total erase yes yes block erase no yes programming control program * (2) (1) (2) (3) (1) erase/erase-verify (2) program/program-verify (3) emulation note: * to be provided by the user, in accordance with the recommended algorithm. 527 15.4.7 block divisions the flash memory is divided into two 32-kbyte blocks, one 28-kbyte block, one 16-kbyte block, two 8-kbyte blocks, and four 1-kbyte blocks. address h'00000 address h'1ffff 128 kbytes 1 kbyte 4 28 kbytes 16 kbytes 8 kbytes 8 kbytes 32 kbytes 32 kbytes figure 15-8 flash memory blocks 528 15.5 pin configuration the flash memory is controlled by means of the pins shown in table 15-4. table 15-4 pin configuration pin name abbreviation i/o function reset res input reset flash write enable fwe input flash program/erase protection by hardware mode 2 md2 input sets lsi operating mode mode 1 md1 input sets lsi operating mode mode 0 md0 input sets lsi operating mode port f0 pf0 input sets lsi operating mode when md2 = md1 = md0 = 0 port 16 p16 input sets lsi operating mode when md2 = md1 = md0 = 0 port 14 p14 input sets lsi operating mode when md2 = md1 = md0 = 0 transmit data txd2 output serial transmit data output receive data rxd2 input serial receive data input 529 15.6 register configuration the registers used to control the on-chip flash memory when enabled are shown in table 15-5. in order to access these registers, the flshe bit in scrx must be set to 1 (except for ramer, scrx). table 15-5 register configuration register name abbreviation r/w initial value address * 1 flash memory control register 1 flmcr1 * 5 r/w * 2 h'00 * 3 h'ffa8 flash memory control register 2 flmcr2 * 5 r * 2 h'00 h'ffa9 erase block register 1 ebr1 * 5 r/w * 2 h'00 * 4 h'ffaa erase block register 2 ebr2 * 5 r/w * 2 h'00 * 4 h'ffab ram emulation register ramer * 5 r/w h'00 h'fedb serial control register x scrx r/w h'00 h'fdb4 notes: *1 lower 16 bits of the address. *2 to access these registers, set the flshe bit to 1 in serial control register x. even if flshe is set to 1, if the chip is in a mode in which the on-chip flash memory is disabled, a read will return h'00 and writes are invalid. writes are also invalid when the fwe bit in flmcr1 is not set to 1. *3 when a high level is input to the fwe pin, the initial value is h'80. *4 when a low level is input to the fwe pin, or if a high level is input and the swe1 bit in flmcr1 is not set, these registers are initialized to h'00. *5 flmcr1, flmcr2, ebr1, ebr2, and ramer are 8-bit registers. only byte access can be used on these registers, with the access requiring two states. these registers are for use exclusively by the flash memory version. reads to the corresponding addresses in the mask rom version will return an undefined value, and writes to these addresses are invalid. 530 15.7 register descriptions 15.7.1 flash memory control register 1 (flmcr1) bit: 7 6 5 4 3 2 1 0 fwe swe1 esu1 psu1 ev1 pv1 e1 p1 initial value: * 00 00 0 00 r/w: r r/w r/w r/w r/w r/w r/w r/w note: * determined by the state of the fwe pin. flmcr1 is an 8-bit register used for flash memory operating mode control. program-verify mode or erase-verify mode for addresses h'00000 to h'1ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the pv1 or ev1 bit. program mode for addresses h'00000 to h'1ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the psu1 bit, and finally setting the p1 bit. erase mode for addresses h'00000 to h'1ffff is entered by setting swe1 bit to 1 when fwe = 1, then setting the esu1 bit, and finally setting the e1 bit. flmcr1 is initialized by a power-on reset, and in hardware standby mode and software standby mode. its initial value is h'80 when a high level is input to the fwe pin, and h'00 when a low level is input. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. writes are enabled only in the following cases: writes to bit swe1 of flmcr1 enabled when fwe = 1, to bits esu1, psu1, ev1, and pv1 when fwe = 1 and swe1 = 1, to bit e1 when fwe = 1, swe1 = 1 and esu1 = 1, and to bit p1 when fwe = 1, swe1 = 1, and psu1 = 1. bit 7flash write enable bit (fwe): sets hardware protection against flash memory programming/erasing. bit 7 fwe description 0 when a low level is input to the fwe pin (hardware-protected state) 1 when a high level is input to the fwe pin 531 bit 6software write enable bit 1 (swe1): enables or disables flash memory programming and erasing. set this bit when setting bits 5 to 0, bits 7 to 0 of ebr1, and bits 3 to 0 of ebr2. bit 6 swe1description 0 writes disabled (initial value) 1 writes enabled [setting condition] when fwe = 1 bit 5erase setup bit 1 (esu1): prepares for a transition to erase mode. set this bit to 1 before setting the e1 bit in flmcr1 to 1. do not set the swe1, psu1, ev1, pv1, e1, or p1 bit at the same time. bit 5 esu1description 0 erase setup cleared (initial value) 1 erase setup [setting condition] when fwe = 1 and swe1 = 1 bit 4program setup bit 1 (psu1): prepares for a transition to program mode. set this bit to 1 before setting the p1 bit in flmcr1 to 1. do not set the swe1, esu1, ev1, pv1, e1, or p1 bit at the same time. bit 4 psu1description 0 program setup cleared (initial value) 1 program setup [setting condition] when fwe = 1 and swe1 = 1 532 bit 3erase-verify 1 (ev1): selects erase-verify mode transition or clearing. do not set the swe1, esu1, psu1, pv1, e1, or p1 bit at the same time. bit 3 ev1description 0 erase-verify mode cleared (initial value) 1 transition to erase-verify mode [setting condition] when fwe = 1 and swe1 = 1 bit 2program-verify 1 (pv1): selects program-verify mode transition or clearing. do not set the swe1, esu1, psu1, ev1, e1, or p1 bit at the same time. bit 2 pv1description 0 program-verify mode cleared (initial value) 1 transition to program-verify mode [setting condition] when fwe = 1 and swe1 = 1 bit 1erase 1 (e1): selects erase mode transition or clearing. do not set the swe1, esu1, psu1, ev1, pv1, or p1 bit at the same time. bit 1 e1description 0 erase mode cleared (initial value) 1 transition to erase mode [setting condition] when fwe = 1, swe1 = 1, and esu1 = 1 533 bit 0program 1 (p1): selects program mode transition or clearing. do not set the swe1, psu1, esu1, ev1, pv1, or e1 bit at the same time. bit 0 p1description 0 program mode cleared (initial value) 1 transition to program mode [setting condition] when fwe = 1, swe1 = 1, and psu1 = 1 15.7.2 flash memory control register 2 (flmcr2) bit: 7 6 5 4 3 2 1 0 fler initial value: 0 0 0 0 0 0 0 0 r/w: r r r r r r r r note: flmcr2 is a read-only register, and should not be written to. flmcr2 is an 8-bit register used for flash memory operating mode control. flmcr2 is initialized to h'00 by a power-on reset, and in hardware standby mode and software standby mode. when on-chip flash memory is disabled, a read will return h'00. bit 7flash memory error (fler): indicates that an error has occurred during an operation on flash memory (programming or erasing). when fler is set to 1, flash memory goes to the error- protection state. bit 7 fler description 0 flash memory is operating normally (initial value) flash memory program/erase protection (error protection) is disabled [clearing condition] power-on reset or hardware standby mode 1 an error has occurred during flash memory programming/erasing flash memory program/erase protection (error protection) is enabled [setting condition] see 15.10.3 error protection bits 6 to 0reserved: these bits always read 0. 534 15.7.3 erase block register 1 (ebr1) bit: 7 6 5 4 3 2 1 0 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ebr1 is an 8-bit register that specifies the flash memory erase area block by block. ebr1 is initialized to h'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin, and when a high level is input to the fwe pin and the swe1 bit in flmcr1 is not set. when a bit in ebr1 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. the flash memory block configuration is shown in table 15-5. 15.7.4 erase block register 2 (ebr2) bit: 7 6 5 4 3 2 1 0 eb9eb8 initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w ebr2 is an 8-bit register that specifies the flash memory erase area block by block. ebr2 is initialized to h'00 by a power-on reset, in hardware standby mode and software standby mode, when a low level is input to the fwe pin. bit 0 will be initialized to 0 if bit swe1 of flmcr1 is not set, even though a high level is input to pin fwe. when a bit in ebr2 is set to 1, the corresponding block can be erased. other blocks are erase-protected. only one of the bits of ebr1 and ebr2 combined can be set. do not set more than one bit, as this will cause all the bits in both ebr1 and ebr2 to be automatically cleared to 0. bits 7 to 2 are reserved and must only be written with 0. when on-chip flash memory is disabled, a read will return h'00, and writes are invalid. 535 the flash memory block configuration is shown in table 15-6. table 15-6 flash memory erase blocks block (size) addresses eb0 (1 kbyte) h'000000Ch'0003ff eb1 (1 kbyte) h'000400Ch'0007ff eb2 (1 kbyte) h'000800Ch'000bff eb3 (1 kbyte) h'000c00Ch'000fff eb4 (28 kbytes) h'001000Ch'007fff eb5 (16 kbytes) h'008000Ch'00bfff eb6 (8 kbytes) h'00c000Ch'00dfff eb7 (8 kbytes) h'00e000Ch'00ffff eb8 (32 kbytes) h'010000Ch'017fff eb9 (32 kbytes) h'018000Ch'01ffff 15.7.5 ram emulation register (ramer) bit: 7 6 5 4 3 2 1 0 rams ram1 ram0 initial value: 0 0 0 0 0 0 0 0 r/w: r r r r/w r/w r/w r/w r/w ramer specifies the area of flash memory to be overlapped with part of ram when emulating real-time flash memory programming. ramer initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset and in software standby mode. ramer settings should be made in user mode or user program mode. flash memory area divisions are shown in table 15-7. to ensure correct operation of the emulation function, the rom for which ram emulation is performed should not be accessed immediately after this register has been modified. normal execution of an access immediately after register modification is not guaranteed. bits 7 to 5reserved: these bits always read 0. bit 4reserved: only 0 may be written to these bits. 536 bit 3ram select (rams): specifies selection or non-selection of flash memory emulation in ram. when rams = 1, all flash memory block are program/erase-protected. bit 3 rams description 0 emulation not selected (initial value) program/erase-protection of all flash memory blocks is disabled 1 emulation selected program/erase-protection of all flash memory blocks is enabled bit 2reserved: only 0 should be written to this bit. bits 1 and 0flash memory area selection: these bits are used together with bit 3 to select the flash memory area to be overlapped with ram. (see table 15-7.) table 15-7 flash memory area divisions addresses block name rams ram1ram0 h'ffd000Ch'ffd3ff ram area 1 kbyte 0 ** h'000000Ch'0003ff eb0 (1 kbyte) 1 0 0 h'000400Ch'0007ff eb1 (1 kbyte) 1 0 1 h'000800Ch'000bff eb2 (1 kbyte) 1 1 0 h'000c00Ch'000fff eb3 (1 kbyte) 1 1 1 * : dont care 15.7.6 serial control register x (scrx) bit: 7 6 5 4 3 2 1 0 flshe initial value: 0 0 0 0 0 0 0 0 r/w: r/w r/w r/w r/w r/w r/w r/w r/w scrx is an 8-bit readable/writable register that performs register access control, and on-chip flash memory control (including the f-ztat version). scrx is initialized to h'00 by a reset and in hardware standby mode. bits 7 to 4reserved: only 0 should be written to these bits. 537 bit 3flash memory control register enable (flshe): controls cpu access to the flash memory control registers (flmcr1, flmcr2, ebr1, and ebr2). setting the flshe bit to 1 enables read/write access to the flash memory control registers. if flshe is cleared to 0, the flash memory control registers are deselected. in this case, the flash memory control register contents are retained. when the flshe bit is set to 1, the flash memory control registers can be read and written to. when flshe is cleared to 0, the flash memory control registers are deselected. in this case, the contents of the flash memory control registers are retained. bit 3 flshe description 0 flash control registers deselected in area h'ffffa8 to h'ffffac (initial value) 1 flash control registers selected in area h'ffffa8 to h'ffffac bits 2 to 0reserved: only 0 should be written to these bits. 538 15.8 on-board programming modes when pins are set to on-board programming mode and a reset-start is executed, a transition is made to the on-board programming state in which program/erase/verify operations can be performed on the on-chip flash memory. there are two on-board programming modes: boot mode and user program mode. the pin settings for transition to each of these modes are shown in table 15-8. for a diagram of the transitions to the various flash memory modes, see figure 15-3. table 15-8 setting on-board programming modes mode fwe md2 md1md0 boot mode expanded mode 1010 single-chip mode 0 1 1 user program mode expanded mode 1110 single-chip mode 1 1 1 15.8.1 boot mode when boot mode is used, the flash memory programming control program must be prepared in the host beforehand. the sci channel to be used is set to asynchronous mode. when a reset-start is executed after the h8s/2214s pins have been set to boot mode, the boot program built into the h8s/2214 is started and the programming control program prepared in the host is serially transmitted to the h8s/2214 via the sci. in the h8s/2214, the programming control program received via the sci is written into the programming control program area in on- chip ram. after the transfer is completed, control branches to the start address of the programming control program area and the programming control program execution state is entered (flash memory programming is performed). the transferred programming control program must therefore include coding that follows the programming algorithm given later. the system configuration in boot mode is shown in figure 15-9, and the boot mode execution procedure in figure 15-10. 539 rxd2 txd2 sci2 h8s/2214 flash memory write data reception verify data transmission host on-chip ram figure 15-9 system configuration in boot mode if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error indication, and the erase operation and subsequent operations are halted. when a transition is made to boot mode, or from boot mode to another mode, mode switching must be carried out by means of res input. the states of ports with multiplexed address functions and bus control output signals ( as , rd , wr ) change during the switchover period (while a low level is being input at the res pin), and therefore these pins should not be used for output signals during this period. 540 note: if a memory cell does not operate normally and cannot be erased, one h'ff byte is transmitted as an erase error, and the erase operation and subsequent operations are halted. start set pins to boot mode and execute reset-start host transfers data (h'00) continuously at prescribed bit rate h8s/2214 measures low period of h'00 data transmitted by host h8s/2214 calculates bit rate and sets value in bit rate register after bit rate adjustment, h8s/2214 transmits one h'00 data byte to host to indicate end of adjustment host confirms normal reception of bit rate adjustment end indication (h'00), and transmits one h'55 data byte after receiving h'55, h8s/2214 transmits one h'aa data byte to host host transmits number of programming control program bytes (n), upper byte followed by lower byte h8s/2214 transmits received number of bytes to host as verify data (echo-back) n = 1 host transmits programming control program sequentially in byte units h8s/2214 transmits received programming control program to host as verify data (echo-back) transfer received programming control program to on-chip ram n = n? no yes end of transmission check flash memory data, and if data has already been written, erase all blocks after confirming that all flash memory data has been erased, h8s/2214 transmits one h'aa data byte to host execute programming control program transferred to on-chip ram n + 1 n figure 15-10 boot mode execution procedure 541 automatic sci bit rate adjustment start bit stop bit d0 d1 d2 d3 d4 d5 d6 d7 low period (9 bits) measured (h'00 data) high period ( 1 or more bits ) figure 15-11 automatic sci bit rate adjustment when boot mode is initiated, the h8s/2214 measures the low period of the asynchronous sci communication data (h'00) transmitted continuously from the host. the sci transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. the h8s/2214 calculates the bit rate of the transmission from the host from the measured low period, and transmits one h'00 byte to the host to indicate the end of bit rate adjustment. the host should confirm that this adjustment end indication (h'00) has been received normally, and transmit one h'55 byte to the h8s/2214. if reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. depending on the hosts transmission bit rate and the h8s/2214s system clock frequency, there will be a discrepancy between the bit rates of the host and the h8s/2214. set the host transfer bit rate at 4800, 9600, or 19,200 bps to operate the sci properly. table 15-9 shows host transfer bit rates and system clock frequencies for which automatic adjustment of the h8s/2214 bit rate is possible. the boot program should be executed within this system clock range. table 15-9 system clock frequencies for which automatic adjustment of h8s/2214 bit rate is possible host bit rate system clock frequency for which automatic adjustment of lsi bit rate is possible 4,800 bps 2 mhz to 16 mhz 9,600 bps 4 mhz to 16 mhz 19,200 bps 8 mhz to 16 mhz 542 on-chip ram area divisions in boot mode: in boot mode, the ram area is divided into an area used by the boot program and an area to which the programming control program is transferred via the sci, as shown in figure 15-12. the boot program area cannot be used until the execution state in boot mode switches to the programming control program transferred from the host. h'ffc000 h'ffdfff h'ffe000 h'ffefbf programming control program area (8 kbytes) boot program area (4 kbytes) note: the boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to ram. note also that the boot program remains in this area of the on-chip ram even after control branches to the programming control program. figure 15-12 ram areas in boot mode notes on use of boot mode: ? when the chip comes out of reset in boot mode, it measures the low-level period of the input at the scis rxd2 pin. the reset should end with rxd2 high. after the reset ends, it takes approximately 100 states before the chip is ready to measure the low-level period of the rxd2 pin. ? in boot mode, if any data has been programmed into the flash memory (if all data is not 1), all flash memory blocks are erased. boot mode is for use when user program mode is unavailable, such as the first time on-board programming is performed, or if the program activated in user program mode is accidentally erased. ? interrupts cannot be used while the flash memory is being programmed or erased. ? the rxd2 and txd2 pins should be pulled up on the board. ? before branching to the programming control program (ram area h'ffc000), the chip terminates transmit and receive operations by the on-chip sci (channel 2) (by clearing the re 543 and te bits in scr to 0), but the adjusted bit rate value remains set in brr. the transmit data output pin, txd2, goes to the high-level output state (pa1ddr = 1, pa1dr = 1). the contents of the cpus internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. in particular, since the stack pointer (sp) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. initial settings must also be made for all other on-chip registers. ? boot mode can be entered by making the pin settings shown in table 15-8 and executing a reset-start. boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then setting the fwe pin and mode pins, and executing reset release* 1 . boot mode can also be cleared by a wdt overflow reset. do not change the mode pin input levels in boot mode, and do not drive the fwe pin low while the boot program is being executed or while flash memory is being programmed or erased* 2 . ? if the mode pin input levels are changed (for example, from low to high) during a reset, the state of ports with multiplexed address functions and bus control output pins ( as , rd , hwr ) will change according to the change in the microcomputers operating mode* 3 . therefore, care must be taken to make pin settings to prevent these pins from becoming output signal pins during a reset, or to prevent collision with signals outside the microcomputer. notes: *1 mode pin and fwe pin input must satisfy the mode programming setup time (t mds = 200 ns) with respect to the reset release timing. *2 for further information on fwe application and disconnection, see section 15.15, flash memory programming and erasing precautions. *3 see appendix d, pin states. 15.8.2 user program mode when set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of fwe control and supply of programming data, and storing a program/erase control program in part of the program area as necessary. to select user program mode, select a mode that enables the on-chip flash memory (mode 6 or 7), and apply a high level to the fwe pin. in this mode, on-chip supporting modules other than flash memory operate as they normally would in modes 6 and 7. 544 the flash memory itself cannot be read while the swe bit is set to 1 to perform programming or erasing, so the control program that performs programming and erasing should be run in on-chip ram or external memory. figure 15-13 shows the procedure for executing the program/erase control program when transferred to on-chip ram. clear fwe * fwe = high * branch to flash memory application program branch to program/erase control program in ram area execute program/erase control program (flash memory rewriting) transfer program/erase control program to ram md2, md1, md0 = 110, 111 reset-start write the fwe assessment program and transfer program (and the program/erase control program if necessary) beforehand notes: do not apply a constant high level to the fwe pin. apply a high level to the fwe pin only when the flash memory is programmed or erased. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. * for further information on fwe application and disconnection, see section 15.16, flash memory programming and erasing precautions. figure 15-13 user program mode execution procedure 545 15.9 programming/erasing flash memory a software method, using the cpu, is employed to program and erase flash memory in the on- board programming modes. there are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. transitions to these modes are made by setting the psu1, esu1, p1, e1, pv1, and ev1 bits in flmcr1 for addresses h'000000 to h'01ffff. the flash memory cannot be read while it is being written or erased. install the program to control flash memory programming and erasing (programming control program) in the on-chip ram, in external memory, and execute the program from there. notes: 1. operation is not guaranteed if bits swe1, esu1, psu1, ev1, pv1, e1, and p1 of flmcr1 are set/reset by a program in flash memory in the corresponding address areas. 2. when programming or erasing, set fwe to 1 (programming/erasing will not be executed if fwe = 0). 3. programming should be performed in the erased state. do not perform additional programming on previously programmed addresses. 15.9.1 program mode follow the procedure shown in the program/program-verify flowchart in figure 15-10 to write data or programs to flash memory. performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. programming should be carried out 128 bytes at a time. for the wait times (t sswe , t spsu , t sp10 , t sp30 , t sp200 , t cp , t cpsu , t spv , t spvr , t cpv , t cswe ) after bits are set or cleared in flash memory control register 1 (flmcr1) and the maximum number of programming operations (n), see section 18.6, flash memory characteristics. following the elapse of t sswe s or more after the swe1 bit is set to 1 in flash memory control register 1 (flmcr1), 128-byte data is stored in the program data area and reprogram data area, and the 128-byte data in the program data area in ram is written consecutively to the write addresses. the lower 8 bits of the first address written to must be h'00 or h'80. 128 consecutive byte data transfers are performed. the program address and program data are latched in the flash memory. a 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, h'ff data must be written to the extra addresses. next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. set a value greater than (t spsu + t sp200 + t cp + t cpsu ) s as the wdt overflow period. after this, preparation for program mode (program setup) is carried out by setting the psu1 bit in flmcr1, and after the elapse of t spsu s or more, the operating mode is switched to program mode by 546 setting the p1 bit in flmcr1. the time during which the p1 bit is set is the flash memory programming time. set the programming time according to the table in the programming flowchart. 15.9.2 program-verify mode in program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. after the elapse of a given programming time, the programming mode is exited (the p1 bit in flmcr1 is cleared, then the psu1 bit is cleared at least t cp s later). the watchdog timer is cleared after the elapse of t cpsu s or more, and the operating mode is switched to program-verify mode by setting the pv1 bit in flmcr1. before reading in program-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of t spv s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least t spvr s after the dummy write before performing this read operation. next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 15-14) and transferred to the reprogram data area. after 128 bytes of data have been verified, exit program-verify mode, wait for at least t cpv s, then clear the swe1 bit in flmcr1 to 0. if reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. however, ensure that the program/program-verify sequence is not repeated more than (n) times on the same bits. 547 start programming end return set swe1 bit in flmcr1 wait: t sswe n = 1 m = 0 subroutine call note * 6: write pulse width start of subroutine set psu1 bit in flmcr1 enable wdt set p1 bit in flmcr1 wait: t spsu clear p1 bit in flmcr1 wait: t sp10 or t sp200 clear psu1 bit in flmcr1 wait: t cp disable wdt wait: t cpsu subroutine: write pulse no subroutine call see note * 6 for pulse width no no no no no yes yes yes yes yes yes wait: t spv wait: t spvr * 2 * 4 * 1 * 5 * 1 write pulse (t sp10 ) set pv1 bit in flmcr1 perform h'ff dummy-write to verify address read verify data write data = verify data? 6 n? 6 n? * 4 * 4 * 3 compute additional-programming data wait: t cswe m = 1 128 byte data verify complete? m = 0? increment address programming failure wait: t cswe clear swe1 bit in flmcr1 clear swe1 bit in flmcr1 n 1000? reprogram data (x') 00 0 01 1 10 1 11 1 verify data (v) additional-programming data (y) comments additional programming executed additional programming not executed additional programming not executed additional programming not executed successively write 128-byte data from reprogram data area in ram to flash memory write pulse (t sp30 or t sp200 ) ram program data storage area (128 bytes) reprogram data storage area (128 bytes) additional program data storage area (128 bytes) store 128 bytes program data in program data area and reprogram data area number of writes n 1 2 3 4 5 6 7 8 9 10 11 12 13 . . . 998 999 1000 write time (t sp30 /t sp200 ) s t sp30 t sp30 t sp30 t sp30 t sp30 t sp30 t sp200 t sp200 t sp200 t sp200 t sp200 t sp200 t sp200 . . . t sp200 t sp200 t sp200 original data (d) verify data (v) 01 0 10 0 reprogram data (x) comments programming complete. programming is incomplete; reprogramming should be performed. reprogram data computation table 01 1 11 1 left in the erased state. additional-programming data computation table transfer additional-programming data to additional-programming data area compute reprogram data clear pv1 bit in flmcr1 wait: t cpv transfer reprogram data to reprogram data area successively write 128-byte data from additional-programming data area in ram to flash memory n n + 1 note: use a t sp10 write pulse for additional programming. notes: * 1 transfer data in byte units. the lower eight bits of the start address to which data is written must be h'00 or h'80. transfer 128-byte data even when writing fewer than 128 bytes. in this case, set h'ff in unused addresses. * 2 read verify data in longword form (32 bits). * 3 even for bits to which data is already written, an additional write should be performed if their verify result is ng. * 4 a 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional program data must be provided in ram. the reprogram and additional program data contents are modified as programming proceeds. * 5 a write pulse of t sp30 or t sp200 is applied according to the progress of the programming operation. see note 6 for the pulse widths. when writing of the additional program data is executed, a t sp10 write pulse should be applied. reprogram data x' means reprogram data when the pulse is applied. data writes must be performed in the memory-erased state. do not write additional data to an address to which data is already written. figure 15-14 program/program-verify flowchart 548 15.9.3 erase mode flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart shown in figure 15-15. for the wait times (t sswe , t sesu , t se , t ce , t cesu , t sev , t sevr , t cev , t cswe ) after bits are set or cleared in flash memory control register 1 (flmcr1) and the maximum number of erase operations (n), see section 18.6, flash memory characteristics. to perform data or program erasure, make a 1-bit setting for the flash memory area to be erased in erase block register 1 or 2 (ebr1 or ebr2) at least t sswe s after setting the swe1 bit to 1 in flash memory control register 1 (flmcr1). next, set up the watchdog timer to prevent overerasing in the event of program runaway, etc. set a value greater than (t sesu + t se + t ce + t cesu ) s as the wdt overflow period. after this, preparation for erase mode (erase setup) is carried out by setting the esu1 bit in flmcr1, and after the elapse of t sesu s or more, the operating mode is switched to erase mode by setting the e1 bit in flmcr1. the time during which the e1 bit is set is the flash memory erase time. ensure that the erase time does not exceed t se ms. note: with flash memory erasing, prewriting (setting all data in the memory to be erased to 0) is not necessary before starting the erase procedure. 15.9.4 erase-verify mode in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. in erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. after the elapse of the erase time, erase mode is exited (the e1 bit in flmcr1 is cleared to 0, then the esu1 bit is cleared to 0 at least t ce s later), the watchdog timer is cleared after the elapse of t cesu s or more, and the operating mode is switched to erase-verify mode by setting the ev1 bit in flmcr1. before reading in erase-verify mode, a dummy write of h'ff data should be made to the addresses to be read. the dummy write should be executed after the elapse of t sev s or more. when the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. wait at least t sevr s after the dummy write before performing this read operation. if the read data has been erased (all 1), execute a dummy write to the next address, and perform an erase-verify. if the read data has not been erased, set erase mode again and repeat the erase/erase-verify sequence as before. however, ensure that the erase/erase-verify sequence is not repeated more than (n) times. when verification is completed, exit erase-verify mode, and wait for at least t cev s. if erasure has been completed on all the erase blocks, clear the swe1 bit in flmcr1. if there are any unerased blocks, make a 1-bit setting for the flash memory block to be erased, and repeat the erase/erase-verify sequence as before. 549 end of erasing start set swe1 bit in flmcr1 set esu1 bit in flmcr set e1 bit in flmcr1 t sswe : wait 1 s t sesu : wait 100 s n = 1 set ebr1 (2) enable wdt * 3 t se : wait 10 ms t ce : wait 10 s t cesu : wait 10 s t sev : wait 20 s set block start address to verify address t sevr : wait 20 s wait: t cev * 2 * 4 start erase clear e1 bit in flmcr1 clear esu1 bit in flmcr1 set ev1 bit in flmcr1 h'ff dummy write to verify address read verify data clear ev1 bit in flmcr1 wait: t cev clear ev1 bit in flmcr1 wait: t cswe disable wdt halt erase * 1 verify data = all "1"? last address of block? end of erasing of all erase blocks? erase failure wait: t cswe clear swe1 bit in flmcr1 clear swe1 bit in flmcr1 n 100? ng ng ng ng ok ok ok ok n n + 1 increment address notes: * 1 preprogramming (setting erase block data to all "0") is not necessary. * 2 verify data is read in 32-bit (longword) units. * 3 set only one bit in ebr1 (2). more than one bit cannot be set. * 4 erasing is performed in block units. to erase a number of blocks, each block must be erased in turn. erasing must be performed in block units. figure 15-15 erase/erase-verify flowchart 550 15.10 protection there are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 15.10.1 hardware protection hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. hardware protection is reset by settings in flash memory control register 1 (flmcr1), flash memory control register 2 (flmcr2), erase block register 1 (ebr1), and erase block register 2 (ebr2). the flmcr1, flmcr2, ebr1, and ebr2 settings are retained in the error-protected state. (see table 15-10.) table 15-10 hardware protection functions item description program erase fwe pin protection ? when a low level is input to the fwe pin, flmcr1, flmcr2, (except bit fler) ebr1, and ebr2 are initialized, and the program/erase-protected state is entered. yes yes reset/standby protection ? in a power-on reset (including a wdt power-on reset) and in standby mode, flmcr1, flmcr2, ebr1, and ebr2 are initialized, and the program/erase- protected state is entered. ? in a reset via the res pin, the reset state is not entered unless the res pin is held low until oscillation stabilizes after powering on. in the case of a reset during operation, hold the res pin low for the res pulse width specified in the ac characteristics section. yes yes 551 15.10.2 software protection software protection can be implemented by setting the swe1 bit in flmcr1, erase block register 1 (ebr1), erase block register 2 (ebr2), and the rams bit in the ram emulation register (ramer). when software protection is in effect, setting the p1 or e1 bit in flash memory control register 1 (flmcr1), does not cause a transition to program mode or erase mode. (see table 15- 11.) table 15-11 software protection functions item description program erase swe bit protection ? setting bit swe1 in flmcr1 to 0 will place area h'000000 to h'01ffff in the program/erase-protected state. (execute the program in the on-chip ram, external memory) yes yes block specification protection ? erase protection can be set for individual blocks by settings in erase block register 1 (ebr1) and erase block register 2 (ebr2). ? setting ebr1 and ebr2 to h'00 places all blocks in the erase-protected state. yes emulation protection ? setting the rams bit to 1 in the ram emulation register (ramer) places all blocks in the program/erase-protected state. yes yes 552 15.10.3 error protection in error protection, an error is detected when h8s/2214 runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. if the h8s/2214 malfunctions during flash memory programming/erasing, the fler bit is set to 1 in flmcr2 and the error protection state is entered. the flmcr1, flmcr2, ebr1, and ebr2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. program mode or erase mode cannot be re-entered by re-setting the p1 or e1 bit. however, pv1 and ev1 bit setting is enabled, and a transition can be made to verify mode. fler bit setting conditions are as follows: 1. when the flash memory of the relevant address area is read during programming/erasing (including vector read and instruction fetch) 2. immediately after exception handling (excluding a reset) during programming/erasing 3. when a sleep instruction (including software standby) is executed during programming/erasing 4. when the cpu releases the bus to the dtc during programming/erasing. error protection is released only by a power-on reset and in hardware standby mode. 553 figure 15-16 shows the flash memory state transition diagram. rd vf pr er fler = 0 error occurrence res = 0 or hstby = 0 res = 0 or hstby = 0 rd vf pr er fler = 0 program mode erase mode reset or standby (hardware protection) rd vf pr er fler = 1 rd vf pr er fler = 1 error protection mode error protection mode (software standby) software standby mode flmcr1, flmcr2, (except bit fler) ebr1, ebr2 initialization state flmcr1, flmcr2, ebr1, ebr2 initialization state software standby mode release rd: memory read possible vf: verify-read possible pr: programming possible er: erasing possible rd : memory read not possible vf : verify-read not possible pr : programming not possible er : erasing not possible legend res = 0 or hstby = 0 error occurrence (software standby) figure 15-16 flash memory state transitions 554 15.11 flash memory emulation in ram making a setting in the ram emulation register (ramer) enables part of ram to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in ram in real time. after the ramer setting has been made, accesses can be made from the flash memory area or the ram area overlapping flash memory. emulation can be performed in user mode and user program mode. figure 15-17 shows an example of emulation of real-time flash memory programming. start of emulation program end of emulation program tuning ok? yes no set ramer write tuning data to overlap ram execute application program clear ramer write to flash memory emulation block figure 15-17 flowchart for flash memory emulation in ram 555 h'000000 h'000400 h'000800 h'000c00 h'001000 h'01ffff flash memory eb4 to eb9 eb0 eb1 eb2 eb3 h'ffd000 h'ffd3fff on-chip ram this area can be accessed from both the ram area and flash memory area figure 15-18 example of ram overlap operation example in which flash memory block area eb0 is overlapped 1. set bits rams, ram1 to ram0 in ramer to 1, 0, 0, 0, to overlap part of ram onto the area (eb0) for which real-time programming is required. 2. real-time programming is performed using the overlapping ram. 3. after the program data has been confirmed, the rams bit is cleared, releasing ram overlap. 4. the data written in the overlapping ram is written into the flash memory space (eb0). notes: 1. when the rams bit is set to 1, program/erase protection is enabled for all blocks regardless of the value of ram1 to ram0 (emulation protection). in this state, setting the p1 or e1 bit in flash memory control register 1 (flmcr1), will not cause a transition to program mode or erase mode. when actually programming or erasing a flash memory area, the rams bit should be cleared to 0. 2. a ram area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in ram is being used. 3. block area eb0 contains the vector table. when performing ram emulation, the vector table is needed in the overlap ram. 556 15.12 interrupt handling when programming/erasing flash memory all interrupts, including nmi interrupt is disabled when flash memory is being programmed or erased (when the p1 or e1 bit is set in flmcr1), and while the boot program is executing in boot mode* 1 , to give priority to the program or erase operation. there are three reasons for this: 1. interrupt during programming or erasing might cause a violation of the programming or erasing algorithm, with the result that normal operation could not be assured. 2. in the interrupt exception handling sequence during programming or erasing, the vector would not be read correctly* 2 , possibly resulting in mcu runaway. 3. if interrupt occurred during boot program execution, it would not be possible to execute the normal boot mode sequence. for these reasons, in on-board programming mode alone there are conditions for disabling interrupt, as an exception to the general rule. however, this provision does not guarantee normal erasing and programming or mcu operation. all requests, including nmi interrupt, must therefore be restricted inside and outside the mcu when programming or erasing flash memory. nmi interrupt is also disabled in the error-protection state while the p1 or e1 bit remains set in flmcr1. notes: *1 interrupt requests must be disabled inside and outside the mcu until the programming control program has completed programming. *2 the vector may not be read correctly in this case for the following two reasons: ? if flash memory is read while being programmed or erased (while the p1 or e1 bit is set in flmcr1), correct read data will not be obtained (undetermined values will be returned). ? if the interrupt entry in the vector table has not been programmed yet, interrupt exception handling will not be executed correctly. 15.13 flash memory programmer mode programs and data can be written and erased in programmer mode as well as in the on-board programming modes. in programmer mode, flash memory read mode, auto-program mode, auto- erase mode, and status read mode are supported. in auto-program mode, auto-erase mode, and status read mode, a status polling procedure is used, and in status read mode, detailed internal signals are output after execution of an auto-program or auto-erase operation. in programmer mode, set the mode pins to programmer mode (see table 15-12) and input a 12 mhz input clock. table 15-12 shows the pin settings for programmer mode. for the pin names in programmer mode, see section 1.3.2, pin functions in each operating mode. 557 table 15-12 programmer mode pin settings pin names settings mode pins: md2, md1, md0 low level input to md2, md1, and md0. mode setting pins: pf0, p16, p14, pf3 high level input to pf3, pf0, low level input to p16 and p14 fwe pin high level input (in auto-program and auto-erase modes) res pin power-on reset circuit xtal, extal pins oscillator circuit 15.13.1 socket adapter pin correspondence diagram connect the socket adapter to the chip as shown in figure 15-20. this will enable conversion to a 40-pin arrangement. the on-chip rom memory map is shown in figure 15-19, and the socket adapter pin correspondence diagram in figure 15-20. h'000000 addresses in mcu mode addresses in programmer mode h'01ffff h'00000 h'1ffff on-chip rom space 128 kb figure 15-19 on-chip rom memory map 558 h8s/2214 socket adapter (conversion to 40-pin arrangement) tfp-100b, tfp-100g tbp-112 pin no. pin name 13 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 4 5 6 7 8 9 10 11 3 1 2 66 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 d0 d1 d2 d3 d4 d5 d6 d7 ce oe we fwe f1 g1 g2 g3 h1 g4 h2 j1 h3 j2 k1 j3 k2 l2 h4 k3 l3 j4 k4 c2 c1 d3 d2 d1 e4 e3 e1 d4 b2 b1 e10 g8 f11 e11 other than the above hn27c4096hg (40 pins) pin no. pin name 21 22 23 24 25 26 27 28 29 31 32 33 34 35 36 37 38 39 10 19 18 17 16 15 14 13 12 2 20 3 4 1,40 11,30 5,6,7 8 9 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 ce oe we fwe v cc v ss nc a20 a19 59 63 65 other than the above res xtal extal nc (open) 12, 53, 54, 58, 60, 61, 62, 75, 99, 72 14, 38, 40, 42, 55, 56, 64, 67, 100 e2, f3, h8, c9, f9, g9, g10, j10, g11, h11, d9 a2, f2, f4, j6, k6, k7, l7, f8, e9, h9, f10, j11 v cc v ss power-on reset circuit oscillator circuit legend fwe: flash write enable i/o7Ci/o0: data input/output a18Ca0: address input ce : chip enable oe : output enable we : write enable figure 15-20 socket adapter pin correspondence diagram 559 15.13.2 programmer mode operation table 15-13 shows how the different operating modes are set when using programmer mode, and table 15-14 lists the commands used in programmer mode. details of each mode are given below. ? memory read mode memory read mode supports byte reads. ? auto-program mode auto-program mode supports programming of 128 bytes at a time. status polling is used to confirm the end of auto-programming. ? auto-erase mode auto-erase mode supports automatic erasing of the entire flash memory. status polling is used to confirm the end of auto-programming. ? status read mode status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the i/o6 signal. in status read mode, error information is output if an error occurs. table 15-13 settings for various operating modes in programmer mode pin names mode fwe ce oe we i/o7C i/o0 a18Ca0 read h or l l l h data output ain output disable h or l l h h hi-z x command write h or l l h l data input * ain chip disable h or l h x x hi-z x notes: 1. chip disable is not a standby state; internally, it is an operation state. 2. * ain indicates that there is also address input in auto-program mode. 3. for command writes in auto-program and auto-erase modes, input a high level to the fwe pin. 560 table 15-14 programmer mode commands number 1st cycle 2nd cycle command name of cycles mode address data mode address data memory read mode 1 + n write x h'00 read ra dout auto-program mode 129 write x h'40 write wa din auto-erase mode 2 write x h'20 write x h'20 status read mode 2 write x h'71 write x h'71 notes: 1. in auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. 2. in memory read mode, the number of cycles depends on the number of address write cycles (n). 15.13.3 memory read mode 1. after completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. when reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. 2. in memory read mode, command writes can be performed in the same way as in the command wait state. 3. once memory read mode has been entered, consecutive reads can be performed. 4. after powering on, memory read mode is entered. table 15-15 ac characteristics in transition to memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns 561 ce oe ce a18Ca0 oe we i/o7Ci/o0 note: data is latched on the rising edge of we . t ceh t wep t f t r t ces t nxtc address stable t ds t dh command write memory read mode figure 15-21 timing waveforms for memory read after memory write table 15-16 ac characteristics in transition from memory read mode to another mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns we rise time t r 30 ns we fall time t f 30 ns 562 ce a18Ca0 oe we i/o7Ci/o0 note: do not enable we and oe at the same time. t ceh t wep t f t r t ces t nxtc address stable t ds t dh other mode command write memory read mode figure 15-22 timing waveforms in transition from memory read mode to another mode table 15-17 ac characteristics in memory read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes access time t acc 20 s ce output delay time t ce 150 ns oe output delay time t oe 150 ns output disable delay time t df 100 ns data output hold time t oh 5ns ce a18Ca0 oe we i/o7Ci/o0 v il v il v ih t acc t acc t oh t oh address stable address stable figure 15-23 ce and oe enable state read timing waveforms 563 ce a18Ca0 oe we i/o7Ci/o0 v ih t acc t ce t oe t oe t ce t acc t oh t df t df t oh address stable address stable figure 15-24 ce and oe clock system read timing waveforms 15.13.4 auto-program mode 1. in auto-program mode, 128 bytes are programmed simultaneously. this should be carried out by executing 128 consecutive byte transfers. 2. a 128-byte data transfer is necessary even when programming fewer than 128 bytes. in this case, h'ff data must be written to the extra addresses. 3. the lower 7 bits of the transfer address must be low. if a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. 4. memory address transfer is performed in the second cycle (figure 15-25). do not perform transfer after the third cycle. 5. do not perform a command write during a programming operation. 6. perform one auto-program operation for a 128-byte block for each address. two or more additional programming operations cannot be performed on a previously programmed address block. 7. confirm normal end of auto-programming by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-program operation end decision pin). 8. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . 564 table 15-18 ac characteristics in auto-program mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t wsts 1ms status polling access time t spa 150 ns address setup time t as 0ns address hold time t ah 60 ns memory write time t write 1 3000 ms write setup time t pns 100 ns write end setup time t pnh 100 ns we rise time t r 30 ns we fall time t f 30 ns ce a18Ca0 fwe oe we i/o7 i/o6 i/o5Ci/o0 t pns t wep t ds t dh t f t r t as t ah t wsts t write t spa t ces t ceh t nxtc t nxtc t pnh address stable h'40 h'00 data transfer 1 to 128 bytes write operation end decision signal write normal end decision signal figure 15-25 auto-program mode timing waveforms 565 15.13.5 auto-erase mode 1. auto-erase mode supports only entire memory erasing. 2. do not perform a command write during auto-erasing. 3. confirm normal end of auto-erasing by checking i/o6. alternatively, status read mode can also be used for this purpose (i/o7 status polling uses the auto-erase operation end decision pin). 4. status polling i/o6 and i/o7 pin information is retained until the next command write. as long as the next command write has not been performed, reading is possible by enabling ce and oe . table 15-19 ac characteristics in auto-erase mode (conditions: v cc = 3.3 v 3.0 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes command write cycle t nxtc 20 s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns status polling start time t ests 1ms status polling access time t spa 150 ns memory erase time t erase 100 40000 ms erase setup time t ens 100 ns erase end setup time t enh 100 ns we rise time t r 30 ns we fall time t f 30 ns 566 ce a18Ca0 fwe oe we i/o7 i/o6 i/o5Ci/o0 t ens t wep t ds t dh t f t r t ests t erase t spa t ces t ceh t nxtc t nxtc t pnh h'20 h'20 h'00 decision signal erase normal end decision signal figure 15-26 auto-erase mode timing waveforms 567 15.13.6 status read mode 1. status read mode is provided to identify the kind of abnormal end. use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2. the return code is retained until a command write other than a status read mode command write is executed. table 15-20 ac characteristics in status read mode (conditions: v cc = 3.3 v 0.3 v, v ss = 0 v, t a = 25c 5c) item symbol min max unit notes read time after command write t nxtc 20 s ce hold time t ceh 0ns ce setup time t ces 0ns data hold time t dh 50 ns data setup time t ds 50 ns write pulse width t wep 70 ns oe output delay time t oe 150 ns disable delay time t df 100 ns ce output delay time t ce 150 ns we rise time t r 30 ns we fall time t f 30 ns ce a18Ca0 oe we i/o7Ci/o0 t wep t f t r t oe t df t ds t ds t dh t dh t ces t ceh t ce t ceh t nxtc t nxtc t nxtc t ces h'71 ' () $9 $9 ' - figure 15-27 status read mode timing waveforms 568 table 15-21 status read mode return commands pin name i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1i/o0 attribute normal end decision command error program- ming error erase error program- ming or erase count exceeded effective address error initial value 00000000 indications normal end: 0 abnormal end: 1 command error: 1 otherwise: 0 program- ming error: 1 otherwise: 0 erasing error: 1 otherwise: 0 count exceeded: 1 otherwise: 0 effective address error: 1 otherwise: 0 note: i/o2 and i/o3 are undefined. 15.13.7 status polling 1. the i/o7 status polling flag indicates the operating status in auto-program/auto-erase mode. 2. the i/o6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase mode. table 15-22 status polling output truth table pin name during internal operation abnormal end normal end i/o7 0101 i/o6 0011 i/o0Ci/o5 0000 15.13.8 programmer mode transition time commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. after the programmer mode setup time, a transition is made to memory read mode. table 15-23 stipulated transition times to command wait state item symbol min max unit notes standby release (oscillation stabilization time) t osc1 30 ms programmer mode setup time t bmv 10 ms v cc hold time t dwn 0ms 569 t osc1 t bmv t dwn v cc res fwe memory read mode command wait state auto-program mode auto-erase mode command wait state normal/abnormal end decision note: when using other than the automatic write mode and automatic erase mode, drive the fwe input pin low. figure 15-28 oscillation stabilization time, boot program transfer time, and power-down sequence 15.13.9 notes on memory programming 1. when programming addresses which have previously been programmed, carry out auto- erasing before auto-programming. 2. when performing programming using programmer mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. notes: 1. the flash memory is initially in the erased state when the device is shipped by hitachi. for other chips for which the erasure history is unknown, it is recommended that auto- erasing be executed to check and supplement the initialization (erase) level. 2. auto-programming should be performed once only on the same address block. additional programming cannot be performed on previously programmed address blocks. 570 15.14 flash memory and power-down states in addition to its normal operating state, the flash memory has power-down states in which power consumption is reduced by halting part or all of the internal power supply circuitry. there are three flash memory operating states: (1) normal operating mode: the flash memory can be read and written to. (2) standby mode: all flash memory circuits are halted, and the flash memory cannot be read or written to. state (2) is flash memory power-down state. table 15-24 shows the correspondence between the operating states of the lsi and the flash memory. table 15-24 flash memory operating states lsi operating state flash memory operating state high-speed mode medium-speed mode sleep mode normal mode (read/write) software standby mode hardware standby mode standby mode 15.14.1 note on power-down states when the flash memory is in a power-down state, part or all of the internal power supply circuitry is halted. therefore, a power supply circuit stabilization period must be provided when returning to normal operation. when the flash memory returns to its normal operating state from a power- down state, bits sts2 to sts0 in sbycr must be set to provide a wait time of at least 100 s (power supply stabilization time), even if an oscillation stabilization period is not necessary. 571 15.15 flash memory programming and erasing precautions precautions concerning the use of on-board programming mode, the ram emulation function, and prom mode are summarized below. use the specified voltages and timing for programming and erasing applied voltages in excess of the rating can permanently damage the device. use a prom programmer that supports the hitachi microcomputer device type with 256-kbyte on-chip flash memory (fztat256v3a). do not select the hn27c4096 setting for the prom programmer, and only use the specified socket adapter. failure to observe these points may result in damage to the device. powering on and off (see figures 15-29 to 15-31) do not apply a high level to the fwe pin until v cc has stabilized. also, drive the fwe pin low before turning off v cc . when applying or disconnecting v cc power, fix the fwe pin low and place the flash memory in the hardware protection state. the power-on and power-off timing requirements should also be satisfied in the event of a power failure and subsequent recovery. fwe application/disconnection (see figures 15-29 to 15-31) fwe application should be carried out when mcu operation is in a stable condition. if mcu operation is not stable, fix the fwe pin low and set the protection state. the following points must be observed concerning fwe application and disconnection to prevent unintentional programming or erasing of flash memory: ? apply fwe when the v cc voltage has stabilized within its rated voltage range. ? in boot mode, apply and disconnect fwe during a reset. ? in user program mode, fwe can be switched between high and low level regardless of the reset state. fwe input can also be switched during execution of a program in flash memory. ? do not apply fwe if program runaway has occurred. ? disconnect fwe only when the swe1, esu1, psu1, ev1, pv1, p1, and e bits in flmcr1 are cleared. make sure that the swe1, esu1, psu1, ev1, pv1, p1, and e bits are not set by mistake when applying or disconnecting fwe. 572 do not apply a constant high level to the fwe pin apply a high level to the fwe pin only when programming or erasing flash memory. a system configuration in which a high level is constantly applied to the fwe pin should be avoided. also, while a high level is applied to the fwe pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. use the recommended algorithm when programming and erasing flash memory the recommended algorithm enables programming and erasing to be carried out without subjecting the device to voltage stress or sacrificing program data reliability. when setting the p1 or e1 bit in flmcr1, the watchdog timer should be set beforehand as a precaution against program runaway, etc. do not set or clear the swe1 bit during execution of a program in flash memory wait for at least 100 s after clearing the swe1 bit before executing a program or reading data in flash memory. when the swe1 bit is set, data in flash memory can be rewritten, but access flash memory only for verify operations (verification during programming/erasing). also, do not clear the swe1 bit during programming, erasing, or verifying. similarly, when using emulation by ram with a high level applied to the fwe pin, the swe1 bit should be cleared before executing a program or reading data in flash memory. however, read/write accesses can be performed in the ram area overlapping the flash memory space regardless of whether the swe1 bit is set or cleared. do not use interrupts while flash memory is being programmed or erased all interrupt requests, including nmi, should be disabled during fwe1 application to give priority to program/erase operations. do not perform additional programming. erase the memory before reprogramming in on-board programming, perform only one programming operation on a 128-byte programming unit block. in programmer mode, too, perform only one programming operation on a 128-byte programming unit block. programming should be carried out with the entire programming unit block erased. before programming, check that the chip is correctly mounted in the prom programmer overcurrent damage to the device can result if the index marks on the prom programmer socket, socket adapter, and chip are not correctly aligned. do not touch the socket adapter or chip during programming touching either of these can cause contact faults and write errors. 573 the reset state must be entered after powering on apply the reset signal for at least 100 s during the oscillation settling period. when a reset is applied during operation, this should be done while the swe1 pin is low wait at least 100 s after clearing the swe1 bit before applying the reset. period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) ? v cc fwe t osc1 min 0 s min 0 s t mds * 3 t mds * 3 md 2 to md 0 * 1 res swe bit swe set swe cleared programming/ erasing possible wait time: x wait time: 100 s notes: *1 except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. *2 see section 18.6, flash memory characteristics. *3 mode programming setup time t mds (min) = 200 ns figure 15-29 power-on/off timing (boot mode) 574 swe set swe cleared ? v cc fwe t osc1 min 0 s md 2 to md 0 * 1 res swe bit programming/ erasing possible wait time: x wait time: 100 s t mds * 3 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 2 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) notes: *1 except when switching modes, the level of the mode pins (md2 to md0) must be fixed until power-off by pulling the pins up or down. *2 see section 18.6, flash memory characteristics. *3 mode programming setup time t mds (min) = 200 ns figure 15-30 power-on/off timing (user program mode) 575 period during which flash memory access is prohibited (x: wait time after setting swe bit) * 3 period during which flash memory can be programmed (execution of program in flash memory prohibited, and data reads other than verify operations prohibited) ? v cc fwe t osc1 min 0 s t mds t mds t mds * 2 t resw md 2 to md 0 res swe1 bit mode change * 1 mode change * 1 boot mode user mode user program mode swe set swe cleared programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s programming/erasing possible wait time: x wait time: 100 s user mode user program mode notes: *1 when entering boot mode or making a transition from boot mode to another mode, mode switching must be carried out by means of res input. the state of ports with multiplexed address functions and bus control output pins ( as , rd , wr ) will change during this switchover interval (the interval during which the res pin input is low), and therefore these pins should not be used as output signals during this time. *2 when making a transition from boot mode to another mode, a mode programming setup time t mds (min) of 200 ns is necessary with respect to res clearance timing. *3 see section 18.6, flash memory characteristics. figure 15-31 mode transition timing (example: boot mode user mode ? user program mode) 576 15.16 note on switching from f-ztat version to mask rom version the mask rom version does not have the internal registers for flash memory control that are provided in the f-ztat version. table 15-25 lists the registers that are present in the f-ztat version but not in the mask rom version. if a register listed in table 15-25 is read in the mask rom version, an undefined value will be returned. therefore, if application software developed on the f-ztat version is switched to a mask rom version product, it must be modified to ensure that the registers in table 15-25 have no effect. table 15-25 registers present in f-ztat version but absent in mask rom version register abbreviation address flash memory control register 1 flmcr1 h'ffa8 flash memory control register 2 flmcr2 h'ffa9 erase block register 1 ebr1 h'ffaa erase block register 2 ebr2 h'ffab ram emulation register ramer h'fedb serial control register x scrx h'fdb4 577 section 16 clock pulse generator 16.1 overview the h8s/2214 has a built-in clock pulse generator (cpg) that generates the system clock (?), the bus master clock, and internal clocks. the clock pulse generator consists of a system clock oscillator, duty adjustment circuit, medium- speed clock divider, and bus master clock selection circuit. 16.1.1 block diagram figure 16-1 shows a block diagram of the clock pulse generator. legend: lpwrcr: sckcr: low-power control register system clock control register extal xtal duty adjustment circuit medium- speed clock divider system clock oscillator system clock to ? pin internal clock to supporting modules bus master clock to cpu, dtc, "# % ?/2 to ?/32 ? sck2 to sck0 sckcr rfcut lpwrcr bus master clock selection circuit figure 16-1 block diagram of clock pulse generator 578 16.1.2 register configuration the clock pulse generator is controlled by sckcr and lpwrcr. table 16-1 shows the register configuration. table 16-1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec note: * lower 16 bits of the address. 16.2 register descriptions 16.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs ? clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ? output. description bit 7 highCspeed mode software standby hardware pstop medium-speed mode sleep mode mode, watchstandby mode 0 ? output (initial value) ? output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 and 3reserved: this bit can be read or written to, but only 0 should be written. bits 5 and 4reserved: read-only bits, always read as 0. 579 bits 2 to 0system clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock used in high-speed mode and medium-speed mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 16.2.2 low-power control register (lpwrcr) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 0 r/w 1 stc1 0 r/w bit : initial value : r/w : lpwrcr is an 8-bit readable/writable register that performs power-down mode control. lpwrcr is initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bits 7 to 4reserved: these bits can be read or written to, but only 0 should be written. bit 3built-in feedback resistor control (rfcut): selects whether the oscillators built-in feedback resistor and duty adjustment circuit are used with external clock input. do not access this bit when a crystal oscillator is used. after this bit is set when using external clock input, a transition should intially be made to software standby mode, watch mode, or subactive mode. switching between use and non-use of the oscillators built-in feedback resistor and duty adjustment circuit is performed when the transition is made to software standby mode, watch mode, or subactive mode. 580 bit 3 rfcut description 0 system clock oscillators built-in feedback resistor and duty adjustment circuit are used (initial value) 1 system clock oscillators built-in feedback resistor and duty adjustment circuit are not used bit 2reserved: this bit can be read or written to, but should only be written with 0. bits 1 and 0frequency multiplication factor (stc1, stc0): the stc bits specify the frequency multiplication factor of the pll circuit incorporated into the evaluation chip. the specified frequency multiplication factor is valid after a transition to software standby mode, watch mode, or subactive mode. with the h8s/2214, stc1 and stc0 must both be set to 1. after a reset, stc1 and stc0 are both cleared to 0, and so must be set to 1. bit 1 bit 0 stc1 stc0 description 0 0 x1 (initial value) 1 x2 (setting prohibited) 1 0 x4 (setting prohibited) 1 pll is bypassed 581 16.3 system clock oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 16.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 16-2. select the damping resistance r d according to table 16-2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22 pf figure 16-2 connection of crystal resonator (example) table 16-2 damping resistance value frequency (mhz) 2 4 6 8 10 12 16 r d ( ? ) 1 k 500 300 200 100 0 0 crystal resonator: figure 16-3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 16-3 and the same resonance frequency as the system clock (?). xtal c l at-cut parallel-resonance type extal c 0 lr s figure 16-3 crystal resonator equivalent circuit 582 table 16-3 crystal resonator parameters frequency (mhz) 2 4 6 8 10 12 16 r s max ( ? ) 500 120 100 80 60 60 50 c 0 max (pf) 7 7 7 7 7 7 7 note on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 16-4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 h8s/2214 xtal extal avoid figure 16-4 example of incorrect board design 583 16.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 16-5. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input ( b ) com p lementar y clock in p ut at xtal p in figure 16-5 external clock input (examples) external clock: the external clock signal should have the same frequency as the system clock (?). table 16-4 and figure 16-6 show the input conditions for the external clock. 584 table 16-4 external clock input conditions item symbol min max unit test conditions external clock input lowpulse width t exl 25 ns figure 16-6 external clock input high pulse width t exh 25 ns external clock rise time t exr 6.25 ns external clock fall time t exf 6.25 ns clock low pulse width level t cl 0.4 0.6 t cyc ? 5 mhz figure 18-3 80 ns ? < 5 mhz clock high pulse width level t ch 0.4 0.6 t cyc ? 5 mhz 80 ns ? < 5 mhz the external clock input conditions when the duty adjustment circuit is not used are shown in table 16-5 and figure 16-6. when the duty adjustment circuit is not used, the ? output waveform depends on the external clock input waveform, and so no restrictions apply. table 16-5 external clock input conditions when the duty adjustment circuit is not used item symbol min max unit test conditions external clock input low pulse width t exl 31.25 ns figure 16-6 external clock input high pulse width t exh 31.25 ns external clock rise time t exr 6.25 ns external clock fall time t exf 6.25 ns note: when duty adjustment circuit is not used, the maximum frequency decreases according to the input waveform. (example: when t exl = t exh = 50 ns, and t exr = t exf = 10 ns, clock cycle time = 120 ns; therefore, maximum operating frequency = 8.3 mhz) t exh t exl t exr t exf v cc 0.5 extal figure 16-6 external clock input timing 585 (3) note on switchover of external clock when two or more external clocks (e.g. 10 mhz and 2 mhz) are used as the system clock, switchover of the input clock should be carried out in software standby mode. an example of an external clock switching circuit is shown in figure 16-7, and an example of the external clock switchover timing in figure 16-8. external clock 1 external clock 2 external clock switchover request external interrupt signal external clock switchover signal control circuit h8s/2214 port output external interrupt extal selector figure 16-7 example of external clock switching circuit 200 ns or more (2) (1) (2) (3) (4) ( 5 ) port setting (clock switchover) software standby mode transition external clock switchover external interrupt generation (input interrupt at least 200 ns after transition to software standby mode.) interru p t exce p tion handlin g (5) sleep instruction execution interrupt exception handling operation external clock 1 external clock 2 (1) port setting (3) external clock switchover signal extal internal clock ? (4) wait time external interrupt active (external clock 2) software standby mode active (external clock 1) clock switchover request figure 16-8 example of external clock switchover timing 586 16.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (?). 16.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate ?/2, ?/4, ?/8, ?/16, and ?/32. 16.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock (?) or one of the medium-speed clocks (?/2, ?/4, or ?/8, ?/16, and ?/32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr. 16.7 note on crystal resonator since various characteristics related to the crystal resonator are closely linked to the users board design, thorough evaluation is necessary on the users part, for both the mask versions, and f- ztat versions, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin. 587 section 17 power-down modes 17.1 overview in addition to the normal program execution state, the h8s/2214 has power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the h8s/2214 operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) sleep mode (4) module stop mode (5) software standby mode (6) hardware standby mode of these, (2) to (6) are power-down modes. sleep mode is cpu mode, medium-speed mode is a cpu and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu). certain combinations of these modes can be set. after a reset, the mcu is in high-speed mode. table 17-1 shows the internal chip states in each mode, and table 17-2 shows the conditions for transition to the various modes. figure 17-1 shows a mode transition diagram. 588 table 17-1 h8s/2214 internal states in each mode function high-speed medium- speed sleep module stop software standby hardware standby system clock oscillator functioning functioning functioning functioning halted halted subclock oscillator functioning functioning functioning functioning functioning/ halted halted cpu operation instructions functioning medium- speed halted functioning halted halted registers retained retained undefined ram functioning functioning functioning (dtc) functioning retained retained i/o functioning functioning functioning functioning retained high impedance external interrupts functioning functioning functioning functioning functioning halted on-chip supporting module dmac functioning medium- speed functioning functioning/ halted (retained) halted (retained) halted (reset) operation dtc wdt0 functioning functioning tpu functioning/ halted (retained) sci d/a note: halted (retained) means that internal register values are retained. the internal state is operation suspended. halted (reset) means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). : operating state 589 hardware standby mode stby pin = low notes: ? when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. ? from any state except hardware standby mode, a transition to the power-on reset state occurs whenever res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs whenever mres goes low. ? from any state, a transition to hardware standby mode occurs when stby goes low. sleep mode (main clock) ssby = 0 software standby mode ssby = 1 medium-speed mode (main clock) high-speed mode (main clock) power-on reset state manual reset state stby pin = high res pin = low res pin = high mres = high program execution state reset state sck2 to sck0 0 sck2 to sck0 = 0 program-halted state sleep instruction all interrupt * 1 sleep instruction external interrupt * 2 : transition after exception handling : power-down mode *1 all interrupts *2 nmi, irq0 to irq7 figure 17-1 mode transitions 590 17.1.1 register configuration the power-down modes are controlled by the sbycr, sckcr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 17-2 summarizes these registers. table 17-2 power-down mode registers name abbreviation r/w initial value address * standby control register sbycr r/w h'08 h'fde4 system clock control register sckcr r/w h'00 h'fde6 module stop control register mstpcra r/w h'3f h'fde8 mstpcrb r/w h'ff h'fde9 mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address. 17.2 register descriptions 17.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 2 0 1 0 bit : initial value : r/w : sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7software standby (ssby): specifies a transition to software standby mode. the ssby setting is not changed by a mode transition due to an interrupt, etc. bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction (initial value) transition to subsleep mode after execution of sleep instruction in subactive mode 1 transition to software standby mode after execution of sleep instruction 591 bits 6 to 4standby timer select 2 to 0 (sts2 to sts0): these bits select the time the mcu waits for the clock to stabilize when software standby mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. with crystal oscillation, refer to table 17-4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). with an external clock, any selection can be made*. note: * in the f-ztat version, a 16-state standby time cannot be used with an external clock. use 2048 states or more. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 1 0 standby time = 2048 states 1 standby time = 16 states * note: * cannot be used in the f-ztat version. bit 2 to 0reserved: this bit cannot be modified and is always read as 0. bit 3output port enable (ope): specifies whether the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) retain their output state or go to the high-impedance state in software standby mode. bit 3 ope description 0 in software standby mode, address bus and bus control signals are high-impedance 1 in software standby mode, address bus and bus control signals retain their output state (initial value) 592 17.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit : initial value : r/w : sckcr is an 8-bit readable/writable register that performs ? clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ? output. description bit 7 highCspeed mode software standby hardware pstop medium-speed mode sleep mode mode, watch standby mode 0 ? output (initial value) ? output fixed high high impedance 1 fixed high fixed high fixed high high impedance bits 6 and 3reserved: these bits can be read or written to, but should only be written with 0. bits 5 and 4reserved: these bits cannot be modified and are always read as 0. bits 2 to 0system clock select 2 to 0 (sck2 to sck0): these bits select the clock for the bus master in high-speed mode and medium-speed mode. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?/2 1 0 medium-speed clock is ?/4 1 medium-speed clock is ?/8 1 0 0 medium-speed clock is ?/16 1 medium-speed clock is ?/32 1 593 17.2.3 module stop control register (mstpcr) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit : initial value : r/w : mstpcra 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit : initial value : r/w : mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit : initial value : r/w : mstpcrc mstpcra, mstpcrb, and mstpcrc are 8-bit readable/writable registers that perform module stop mode control. mstpcra is initialized to h'3f by a reset and in hardware standby mode. mstpcrb and mstpcrc are initialized to h'ff. they are not initialized in software standby mode. 594 mstpcra, mstpcrb, and mstpcrc bits 7 to 0module stop (mstpa7 to mstpa0, mstpb7 to mstpb0, and mstpc7 to mstpc0): these bits specify module stop mode. see table 17-3 for the method of selecting on-chip supporting modules. mstpcra, mstpcrb, and mstpcrc bits 7 to 0 mstpa7 to mstpa0, mstpb7 to mstpb0, and mstpc7 to mstpc0 description 0 module stop mode is cleared (initial value of mstpa7, mstpa6) 1 module stop mode is set (initial value of except mstpa7 to mstpa6) 17.3 medium-speed mode when the sck2 to sck0 bits in sckcr are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. in medium-speed mode, the cpu operates on the operating clock (?/2, ?/4, ?/8, ?/16, or ?/32) specified by the sck2 to sck0 bits. the bus master other than the cpu (the dmac and dtc) also operates in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock (?). in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if ?/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby is cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, a transition is made to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin and mres pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a reset caused by overflow of the watchdog timer. when the stby pin is driven low, a transition is made to hardware standby mode. figure 17-2 shows the timing for transition to and clearance of medium-speed mode. 595 bus master clock ?, supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 17-2 medium-speed mode transition and clearance timing 17.4 sleep mode 17.4.1 sleep mode if a sleep instruction is executed when the ssby bit in sbycr is cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpus internal registers are retained. other supporting modules do not stop. 17.4.2 clearing sleep mode sleep mode is cleared by all interrupts, or with the res pin, mres pin or stby pin. clearing with an interrupt: when an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. sleep mode will not be cleared if interrupts are disabled, or if interrupts other than nmi have been masked by the cpu. clearing with the res pin and mres pin: when the res pin and mres pin is driven low, the reset state is entered. when the res pin and mres pin is driven high after the prescribed reset input period, the cpu begins reset exception handling. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. 596 17.5 module stop mode 17.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 17-3 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. in module stop mode, the internal states of modules are retained. after reset release, all modules other than the dmac and dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. when a transition is made to sleep mode with all modules stopped (mstpcr = h'ffffff), the bus controller and i/o ports also stop operating, enabling current dissipation to be further reduced. 597 table 17-3 mstp bits and corresponding on-chip supporting modules register bit module mstpcra mstpa7 dma controller (dmac) mstpa6 data transfer controller (dtc) mstpa5 16-bit timer pulse unit (tpu) mstpa4 * mstpa3 * mstpa2 * mstpa1 * mstpa0 * mstpcrb mstpb7 serial communication interface 0 (sci0) mstpb6 serial communication interface 1 (sci1) mstpb5 serial communication interface 2 (sci2) mstpb4 * mstpb3 * mstpb2 * mstpb1 * mstpb0 external module expansion function mstpcrc mstpc7 * mstpc6 * mstpc5 d/a converter mstpc4 * mstpc3 * mstpc2 * mstpc1 * mstpc0 * note: * reserved. 17.5.2 usage notes dmac and dtc module stop mode: depending on the operating status of the dmac and dtc, the mstpa7 and mstpa6 bits may not be set to 1. setting of the dtc module stop mode should be carried out only when the dtc is not activated. for details, section 7, dma controller (dmac) and section 8, data transfer controller (dtc). on-chip supporting module interrupts: relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been 598 requested, it will not be possible to clear the cpu interrupt source, dmac, or dtc activation source. interrupts should therefore be disabled before setting module stop mode. writing to mstpcr: mstpcr should be written to only by the cpu. 17.6 software standby mode 17.6.1 software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, the lson bit in software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpus internal registers, ram data, and the states of on-chip supporting module, and of the i/o ports, are retained. the address bus and bus control signals are placed in the high-impedance state. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 17.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq7 ), or by means of the res pin, mres pin or stby pin. clearing with an interrupt: when an nmi or irq0 to irq7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire h8s/2214 chip, software standby mode is cleared, and interrupt exception handling is started. when software standby mode is cleared with an irq0 to irq7 interrupt, set the corresponding enable bit to 1 and ensure that an interrupt of higher priority than interrupts irq0 to irq7 is not generated. software standby mode cannot be cleared if the interrupt has been masked by the cpu side or has been designated as a dtc activation source. clearing with the res pin and mres pin: when the res pin and mres pin are driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire h8s/2214 chip. note that the res pin and mres pin must be held low until clock oscillation stabilizes. when the res pin and mres pin go high, the cpu begins reset exception handling. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode. 599 17.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 17-4 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 17-4 oscillation stabilization time settings sts2 sts1 sts0 standby time 16 mhz 13 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.51 0.6 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 1.0 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 2.0 2.5 3.3 4.1 5.5 8.2 16.4 1 65536 states 4.1 5.0 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 8.2 10.1 13.1 16.4 21.8 32.8 65.5 1 262144 states 16.4 20.2 26.2 32.8 43.6 65.6 131.2 1 0 2048 states 0.13 0.16 0.2 0.3 0.3 0.5 1.0 1 16 states 1.0 1.2 1.6 2.0 1.7 4.0 8.0 s : recommended time setting using an external clock: any value can be set. normally, use of the minimum time is recommended. note: in the f-ztat version, a 16-state standby time cannot be used with an external clock. use 2048 states or more. 17.6.4 software standby mode application example figure 17-3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin. 600 oscillator ? nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation stabilization time (t osc2 ) nmi exception handling figure 17-3 software standby mode application example 17.6.5 usage notes i/o port states: in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during the oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. 17.7 hardware standby mode 17.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state. 601 in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md2 to md0) while the h8s/2214 is in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillation stabilizes (at least t osc1 the oscillation stabilization timewhen using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 17.7.2 hardware standby mode timing figure 17-4 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator res stby oscillation stabilization time (t osc1 ) reset exception handling figure 17-4 hardware standby mode timing (example) 602 17.8 ? clock output disabling function output of the ? clock can be controlled by means of the pstop bit in sckcr and the corresponding ddr bit. when the pstop bit is set to 1, the ? clock is stopped at the end of the bus cycle, and ? output goes high. ? clock output is enabled when pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, ? clock output is disabled and input port mode is set. table 17-5 shows the state of the ? pin in each processing mode. table 17-5 ? pin state in each processing mode ddr 0 1 1 pstop 0 1 hardware standby mode high impedance high impedance high impedance software standby mode high impedance fixed high fixed high sleep mode high impedance ? output fixed high high-speed mode, medium-speed mode high impedance ? output fixed high 603 section 18 electrical characteristics 18.1 absolute maximum ratings table 18-1 lists the absolute maximum ratings. table 18-1 absolute maximum ratings item symbol value unit power supply voltage v cc C0.3 to +4.6 v programming voltage v pp C0.3 to +13.5 v input voltage (except port 9) v in C0.3 to v cc +0.3 v input voltage (port 9) v in C0.3 to av cc +0.3 v reference voltage v ref C0.3 to av cc +0.3 v analog power supply voltage av cc C0.3 to +4.6 v operating temperature t opr regular specifications: C20 to +75 c wide-range specifications: C40 to +85 c storage temperature t stg C55 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded. 604 18.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 18.1. system clock (1) power supply voltage and oscillation frequency range ? active (high-speed/medium-speed) mode ? sleep mode f (mhz) 16.0 10.0 2.0 0 2.7 3.0 3.6 vcc (v) system clock (2) power supply voltage and instruction execution time range ? active (high-speed/medium-speed) mode (ns) 62.5 100 500 0 2.7 3.0 3.6 vcc (v) figure 18-1 power supply voltage and operating ranges 605 18.3 dc characteristics tables 18-2, 18-3, and 18-4 list the dc characteristics. table 18-5 lists the permissible output currents. table 18-2 dc characteristics (1) condition: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications)* item symbol min typ max unit test conditions schmitt irq7 to irq0 v t C v cc 0.2 v trigger input exirq0 to v t + v cc 0.8 v voltage exirq7 v t + C v t C v cc 0.05 v input high voltage res , stby , nmi, md2 to md0, fwe v ih v cc 0.9 v cc + 0.3 v extal, v cc 0.8 v cc + 0.3 v port 1, 3, 4, 7, a to g port 9 v cc 0.8 av cc + 0.3 v input low voltage res , stby , fwe, md2 to md0 v il C0.3 v cc 0.1 v nmi, extal, port 1, 3, 4, 7, 9, a to g C0.3 v cc 0.2 v output high all output pins v oh v cc C 0.5 v i oh = C200 a voltage v cc C 1.0 v i oh = C1 ma output low all output pins v ol 0.4 v i ol = 0.4 ma voltage 0.4 v i ol = 0.8 ma input leakage res | i in | 1.0 a v in = current stby , nmi, md2 to md0, port 4 1.0 a 0.5 to v cc C 0.5 v port 9 1.0 a v in = 0.5 to av cc C 0.5 v 606 item symbol min typ max unit test conditions three-state leakage current (off state) port 1, 3, 7, a to g ? i tsi ? 1.0 a v in = 0.5 to v cc C 0.5 v mos input pull-up current port a to e Ci p 10 300 a v in = 0 v note: * if the d/a converter is not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref = av cc . 607 table 18-3 dc characteristics (2) conditions: f-ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications)* 1 item symbol min typ max unit test conditions input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25c current dissipation* 2 normal operation i cc * 4 20 v cc = 3.0 v 36.0 v cc = 3.6 v ma f = 16 mhz sleep mode 13 v cc = 3.0 v 26.0 v cc = 3.6 v ma f = 16 mhz all modules stopped 14 ma f = 16 mhz, v cc = 3.0 v (reference values) medium-speed mode (?/32) 9 ma f = 16 mhz, v cc = 3.0 v (reference values) standby mode* 3 1.0 10 a t a 50c 50 50c < t a analog power supply current during d/a conversion al cc 0.01 5 ma av cc = 3.0 v idle 0.01 5 a reference current during d/a conversion al cc 1.0 1.8 ma v ref = 3.0 v idle 0.01 5 a ram standby voltage v ram 2.0 v notes: *1 if the d/a converter is not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref = av cc . *2 current dissipation values are for v ih min = v cc C 0.3 v, v il max = 0.3 v with all output pins unloaded and the on-chip pull-up resistors in the off state. *3 the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. *4 i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.61 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.44 (ma/(mhz v)) v cc f (sleep mode) 608 table 18-4 dc characteristics (3) conditions: mask rom version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications)* 1 item symbol min typ max unit test conditions input res c in 30 pf v in = 0 v capacitance nmi 30 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25c current dissipation* 2 normal operation i cc * 4 20 v cc = 3.0 v 36 v cc = 3.6 v ma f = 16 mhz sleep mode 13 v cc = 3.0 v 26 v cc = 3.6 v ma f = 16 mhz all modules stopped 14 ma f = 16 mhz, v cc = 3.0 v (reference values) medium-speed mode (?/32) 9 ma f = 16 mhz, v cc = 3.0 v (reference values) standby mode* 3 1.0 10 a t a 50c 50 50c < t a analog power supply current during d/a conversion al cc 0.01 5 ma av cc = 3.0 v idle 0.01 5 a reference current during d/a conversion al cc 1.0 1.8 ma v ref = 3.0 v idle 0.01 5 a ram standby voltage v ram 2.0 v notes: *1 if the d/a converter is not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref = av cc . *2 current dissipation values are for v ih min = v cc C 0.3 v, v il max = 0.3 v with all output pins unloaded and the on-chip pull-up resistors in the off state. *3 the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. *4 i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.61 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.44 (ma/(mhz v)) v cc f (sleep mode) 609 table 18-5 permissible output currents conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications)* item symbol min typ max unit permissible output all output pins v cc = 2.7 to 3.6 v i ol 1.0 ma low current (per pin) permissible output total of all v cc = 2.7 to 3.6 v i ol 60ma low current (total) output pins permissible output all output pins v cc = 2.7 to 3.6 v Ci oh 1.0 ma high current (per pin) permissible output total of all v cc = 2.7 to 3.6 v Ci oh 30ma high current (total) output pins note: * to protect chip reliability, do not exceed the output current values in table 18-5. 18.4 ac characteristics figure 18-2 shows, the test conditions for the ac characteristics. 3 v r l r h c lsi output pin c = 30 pf: r l = 2.4 k ? r h = 12 k ? i/o timing test levels ? low level: 0.8 v ? high level: 2.0 v (v cc : 2.7 to 3.6 v) figure 18-2 output load circuit 610 18.4.1 clock timing table 18-6 lists the clock timing table 18-6 clock timing condition : v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item symbol min max unit test conditions clock cycle time t cyc 62.5 500 ns figure 18-3 clock high pulse width t ch 20 ns clock low pulse width t cl 20 ns clock rise time t cr 10ns clock fall time t cf 10ns clock oscillator settling time at reset (crystal) t osc1 20 ms figure 18-4 clock oscillator settling time in software standby (crystal) t osc2 8 ms figure 17-3 external clock output stabilization delay time t dext 500 s figure 18-4 t ch t cf t cyc t cl t cr ? figure 18-3 system clock timing 611 t osc1 t osc1 extal v cc stby res t dext t dext figure 18-4 oscillator settling timing 18.4.2 control signal timing table 18-7 lists the control signal timing. table 18-7 control signal timing condition : v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item symbol min max unit test conditions res setup time t ress 250 ns figure 18-5 res pulse width t resw 20 t cyc mres setup time t mress 250 ns mres pulse width t mresw 20 t cyc nmi setup time t nmis 250 ns figure 18-6 nmi hold time t nmih 10 nmi pulse width (exiting software standby mode) t nmiw 200 ns irq setup time t irqs 250 ns irq hold time t irqh 10 ns irq pulse width (exiting software standby mode) t irqw 200 ns 612 t resw t ress t mress t mress t mresw t ress res mres figure 18-5 reset input timing t irqs t nmis t nmih irq edge input nmi t irqs t irqh irq irq level input t nmiw t irqw figure 18-6 interrupt input timing 613 18.4.3 bus timing table 18-8 lists the bus timing. table 18-8 bus timing condition: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item symbol min max unit test conditions address delay time t ad 50 ns figure 18-7, address setup time t as 0.5 t cyc C 30 ns figure 18-8, figure 18-10 address hold time t ah 0.5 t cyc C 15 ns cs delay time t csd 50 ns figure 18-7, figure 18-8 as delay time t asd 50 ns figure 18-7, figure 18-8, figure 18-10 rd delay time 1 t rsd1 50 ns figure 18-7, figure 18-8 rd delay time 2 t rsd2 50 ns figure 18-7, figure 18-8, figure 18-10 read data setup time t rds 30 ns figure 18-7, figure 18-8, read data hold time t rdh 0 ns figure 18-10 read data access time 2 t acc2 1.5 t cyc C 65 ns figure 18-7 read data access time 3 t acc3 2.0 t cyc C 65 ns figure 18-7, figure 18-10 read data access time 4 t acc4 2.5 t cyc C 65 ns figure 18-8 read data access time 5 t acc5 3.0 t cyc C 65 ns wr delay time 1 t wrd1 50ns wr delay time 2 t wrd2 50 ns figure 18-7, figure 18-8 wr pulse width 1 t wsw1 1.0 t cyc C 30 ns figure 18-7 wr pulse width 2 t wsw2 1.5 t cyc C 30 ns figure 18-8 614 item symbol min max unit test conditions write data delay time t wdd 70 ns figure 18-7, figure 18-8 write data setup time t wds 0.5 t cyc C 30 ns figure 18-8 write data hold time t wdh 0.5 t cyc C 15 ns figure 18-7, figure 18-8 wait setup time t wts 50 ns figure 18-9 wait hold time t wth 10 ns breq setup time t brqs 50 ns figure 18-11 back delay time t bacd 50ns bus-floating time t bzd 80ns 615 t rsd2 t1 t ad as a23 to a0 t asd rd (read) t2 t csd t as t asd t acc2 t as t as t rsd1 t acc3 t rds t rdh t wrd2 t wdd t wsw1 t wdh t ah cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t ah t wrd2 figure 18-7 basic bus timing (two-state access) 616 t rsd2 t2 as a23 to a0 t asd rd (read) t3 t as t ah t asd t acc4 t rsd1 t acc5 t as t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh t ah cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t1 t csd t wdd t ad figure 18-8 basic bus timing (three-state access) 617 tw as a23 to a0 rd (read) t3 cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t2 t wts t1 t wth t wts t wth wait figure 18-9 basic bus timing (three-state access with one wait state) 618 t rsd2 t1 as a23 to a0 t2 t ah t acc3 t rds cs7 to cs0 d15 to d0 (read) t2 or t3 t as t1 t asd t asd t rdh t ad rd (read) figure 18-10 burst rom access timing (two-state access) 619 breq a23 to a0, cs7 to cs0 , t brqs t bacd t bzd t bacd t bzd t brqs back as , rd , hwr , lwr figure 18-11 external bus release timing 620 18.4.4 timing of on-chip supporting modules table 18-9 lists the timing of on-chip supporting modules. table 18-9 timing of on-chip supporting modules condition: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item symbol min max unit test conditions i/o port output data delay time t pwd 100 ns figure 18-12 input data setup time t prs 50 input data hold time t prh 50 tpu timer output delay time t tocd 100 ns figure 18-13 timer input setup time t tics 40 timer clock input setup time t tcks 40 ns figure 18-14 timer clock single edge t tckwh 1.5 t cyc pulse width both edges t tckwl 2.5 sci input clock asynchronous t scyc 4t cyc figure 18-15 cycle synchronous 6 input clock pulse width t sckw 0.4 0.6 t scyc input clock rise time t sckr 1.5 t cyc input clock fall time t sckf 1.5 transmit data delay time t txd 100 ns figure 18-16 receive data setup time (synchronous) t rxs 75 ns receive data hold time (synchronous) t rxh 75 ns 621 ? port 1, 3, 4, 7, 9 a to g (read) t 2 t 1 t pwd t prh t prs port 1, 3, 7 a to g (write) figure 18-12 i/o port input/output timing ? t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 18-13 tpu input/output timing t tcks ? t tcks tclka to tclkd t tckwh t tckwl figure 18-14 tpu clock input timing 622 sck0 to sck3 t sckw t sckr t sckf t scyc figure 18-15 sck clock input timing txd0 to txd3 (transit data) rxd0 to rxd3 (receive data) sck0 to sck3 t rxs t rxh t txd figure 18-16 sci input/output timing (clock synchronous mode) 623 18.4.5 dmac timing table 18-10 lists the dmac timing. table 18-10 dmac timing condition: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item symbol min max unit test conditions dreq setup time t drqs 40 ns figure 18-18 dreq hold time t drqh 10 dreq delay time t ted 50 figure 18-17 t ted tend t 1 t 2 or t 3 t ted figure 18-17 dmac tend output timing t drqs t drqh dreq figure 18-18 dmac dreq output timing 624 18.5 d/a convervion characteristics table 18-11 lists the d/a conversion characteristics. table 18-11 d/a conversion characteristics condition: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc ,v ss = av ss = 0 v, ? = 2 to 16 mhz, t a = C20c to +75c (regular specifications), t a = C40c to +85c (wide-range specifications) item min typ max unit test conditions resolution 8 8 8 bit conversion time 10 s 20-pf capacitive load absolute accuracy 2.0 3.0 lsb 2-m ? resistive load 2.0 lsb 4-m ? resistive load 625 18.6 flash memory characteristics table 18-12 lists the flash memory characteristics. table 18-12 flash memory characteristics conditions: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = av cc , v ss = av ss = 0 v, v cc = 3.0 v to 3.6 v(program/erase operating voltage range), t a = -20c to +75c (program/erase operating temperature range) item symbol min typ max unit test conditions programming time* 1, * 2, * 4 t p 40 200 ms/128 bytes erase time* 1, * 3, * 5 t e 20 1000 ms/block rewrite time n wec 100 times programming wait time after swe1 bit setting* 1 t sswe 11s wait time after psu1 bit setting* 1 t spsu 50 50 s wait time after p1 bit setting* 1, * 4 t sp10 8 1012s t sp30 28 30 32 s 1 n 6 t sp200 198 200 202 s 7 n 1000 wait time after p1 bit clearing* 1 t cp 55s wait time after psu1 bit clearing* 1 t cpsu 55s wait time after pv1 bit setting* 1 t spv 44s wait time after h'ff dummy write* 1 t spvr 22s wait time after pv1 bit clearing* 1 t cpv 22s wait time after swe1 bit clearing* 1 t cswe 100 100 s maximum number of writes* 1, * 4 n1 6 * 4 times n2 994 * 4 times erasing wait time after swe1 bit setting* 1 t sswe 11s wait time after esu1 bit setting* 1 t sesu 100 100 s wait time after e1 bit setting* 1, * 5 t se 10 10 100 ms wait time after e1 bit clearing* 1 t ce 10 10 s wait time after esu1 bit clearing* 1 t cesu 10 10 s wait time after ev1 bit setting* 1 t sev 20 20 s wait time after h'ff dummy write* 1 t sevr 22s wait time after ev1 bit clearing* 1 t sev 44s wait time after swe1 bit clearing* 1 t cswe 100 100 s maximum number of erases* 1, * 5 n 100 times notes: *1 follow the program/erase algorithms when making the time settings. *2 programming time per 128 bytes. (indicates the total time during which the p1 bit is set in flash memory control register 1 (flmcr1). does not include the program-verify time.) 626 *3 time to erase one block. (indicates the time during which the e1 bit is set in flmcr1. does not include the erase-verify time.) *4 maximum programming time. t p (max) = wait time after p1 bit setting (t sp ) maximum number of writes (n) = (t sp30 + t sp10 ) 6 + (t sp200 ) 994 *5 for the maximum erase time (t e ) max), the following relationship applies between the wait time after e1 bit setting (t se ) and the maximum number of erase (n): t e (max) = wait time after e1 bit setting (t se ) maximum number of erases (n) 18.7 usage note although both the f-ztat and mask rom versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip rom, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. therefore, if a system is evaluated using the f-ztat version, a similar evaluation should also be performed using the mask rom version. 627 appendix a instruction set a.1 instruction list operand notation rd general register (destination)* 1 rs general register (source)* 1 rn general register* 1 ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register)* 2 (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + add C subtract multiply divide logical and logical or logical exclusive or transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right ? logical not (logical complement) ( ) < > contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length notes: *1 general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). *2 the mac register cannot be used in the h8s/2214. 628 condition code notation symbol changes according to the result of instruction * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 not affected by execution of the instruction 629 table a-1 data transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.b #xx:8,rd b 2 mov.b rs,rd b 2 mov.b @ers,rd b 2 mov.b @(d:16,ers),rd b 4 mov.b @(d:32,ers),rd b 8 mov.b @ers+,rd b 2 mov.b @aa:8,rd b 2 mov.b @aa:16,rd b 4 mov.b @aa:32,rd b 6 mov.b rs,@erd b 2 mov.b rs,@(d:16,erd) b 4 mov.b rs,@(d:32,erd) b 8 mov.b rs,@-erd b 2 mov.b rs,@aa:8 b 2 mov.b rs,@aa:16 b 4 mov.b rs,@aa:32 b 6 mov.w #xx:16,rd w 4 mov.w rs,rd w 2 mov.w @ers,rd w 2 #xx:8 rd8 0 1 rs8 rd8 0 1 @ers rd8 0 2 @(d:16,ers) rd8 0 3 @(d:32,ers) rd8 0 5 @ers rd8,ers32+1 ers32 0 3 @aa:8 rd8 0 2 @aa:16 rd8 0 3 @aa:32 rd8 0 4 rs8 @erd 0 2 rs8 @(d:16,erd) 0 3 rs8 @(d:32,erd) 0 5 erd32-1 erd32,rs8 @erd 0 3 rs8 @aa:8 0 2 rs8 @aa:16 0 3 rs8 @aa:32 0 4 #xx:16 rd16 0 2 rs16 rd16 0 1 @ers rd16 0 2 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ??????????????????? 630 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.w @(d:16,ers),rd w 4 mov.w @(d:32,ers),rd w 8 mov.w @ers+,rd w 2 mov.w @aa:16,rd w 4 mov.w @aa:32,rd w 6 mov.w rs,@erd w 2 mov.w rs,@(d:16,erd) w 4 mov.w rs,@(d:32,erd) w 8 mov.w rs,@-erd w 2 mov.w rs,@aa:16 w 4 mov.w rs,@aa:32 w 6 mov.l #xx:32,erd l 6 mov.l ers,erd l 2 mov.l @ers,erd l 4 mov.l @(d:16,ers),erd l 6 mov.l @(d:32,ers),erd l 10 mov.l @ers+,erd l 4 mov.l @aa:16,erd l 6 mov.l @aa:32,erd l 8 @(d:16,ers) rd16 0 3 @(d:32,ers) rd16 0 5 @ers rd16,ers32+2 ers32 0 3 @aa:16 rd16 0 3 @aa:32 rd16 0 4 rs16 @erd 0 2 rs16 @(d:16,erd) 0 3 rs16 @(d:32,erd) 0 5 erd32-2 erd32,rs16 @erd 0 3 rs16 @aa:16 0 3 rs16 @aa:32 0 4 #xx:32 erd32 0 3 ers32 erd32 0 1 @ers erd32 0 4 @(d:16,ers) erd32 0 5 @(d:32,ers) erd32 0 7 @ers erd32,ers32+4 @ers32 0 5 @aa:16 erd32 0 5 @aa:32 erd32 0 6 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ??????????????????? 631 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic mov pop push ldm stm movfpe movtpe mov.l ers,@erd l 4 mov.l ers,@(d:16,erd) l 6 mov.l ers,@(d:32,erd) l 10 mov.l ers,@-erd l 4 mov.l ers,@aa:16 l 6 mov.l ers,@aa:32 l 8 pop.w rn w 2 pop.l ern l 4 push.w rn w 2 push.l ern l 4 ldm @sp+,(erm-ern) l 4 stm (erm-ern),@-sp l 4 movfpe @aa:16,rd movtpe rs,@aa:16 ers32 @erd 0 4 ers32 @(d:16,erd) 0 5 ers32 @(d:32,erd) 0 7 erd32-4 erd32,ers32 @ erd 0 5 ers32 @aa:16 0 5 ers32 @aa:32 0 6 @sp rn16,sp+2 sp 0 3 @sp ern32,sp+4 sp 0 5 sp-2 sp,rn16 @sp 0 3 sp-4 sp,ern32 @sp 0 5 (@sp ern32,sp+4 sp) 7/9/11 [1] repeated for each register restored (sp-4 sp,ern32 @sp) 7/9/11 [1] repeated for each register saved [2] [2] operation condition code ihnzvc advanced no. of states * 1 ?????????? ?????????? cannot be used in the h8s/2214 cannot be used in the h8s/2214 632 table a-2 arithmetic instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic add addx adds inc daa sub add.b #xx:8,rd b 2 add.b rs,rd b 2 add.w #xx:16,rd w 4 add.w rs,rd w 2 add.l #xx:32,erd l 6 add.l ers,erd l 2 addx #xx:8,rd b 2 addx rs,rd b 2 adds #1,erd l 2 adds #2,erd l 2 adds #4,erd l 2 inc.b rd b 2 inc.w #1,rd w 2 inc.w #2,rd w 2 inc.l #1,erd l 2 inc.l #2,erd l 2 daa rd b 2 sub.b rs,rd b 2 sub.w #xx:16,rd w 4 rd8+#xx:8 rd8 1 rd8+rs8 rd8 1 rd16+#xx:16 rd16 [3] 2 rd16+rs16 rd16 [3] 1 erd32+#xx:32 erd32 [4] 3 erd32+ers32 erd32 [4] 1 rd8+#xx:8+c rd8 [5] 1 rd8+rs8+c rd8 [5] 1 erd32+1 erd32 1 erd32+2 erd32 1 erd32+4 erd32 1 rd8+1 rd8 1 rd16+1 rd16 1 rd16+2 rd16 1 erd32+1 erd32 1 erd32+2 erd32 1 rd8 decimal adjust rd8 * * 1 rd8-rs8 rd8 1 rd16-#xx:16 rd16 [3] 2 operation condition code ihnzvc advanced no. of states * 1 ??? ? ???????? ?? ????? ???????? ???????? ???????? ?????? ???????? ?? ?? 633 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic sub subx subs dec das mulxu mulxs sub.w rs,rd w 2 sub.l #xx:32,erd l 6 sub.l ers,erd l 2 subx #xx:8,rd b 2 subx rs,rd b 2 subs #1,erd l 2 subs #2,erd l 2 subs #4,erd l 2 dec.b rd b 2 dec.w #1,rd w 2 dec.w #2,rd w 2 dec.l #1,erd l 2 dec.l #2,erd l 2 das rd b 2 mulxu.b rs,rd b 2 mulxu.w rs,erd w 2 mulxs.b rs,rd b 4 mulxs.w rs,erd w 4 rd16-rs16 rd16 [3] 1 erd32-#xx:32 erd32 [4] 3 erd32-ers32 erd32 [4] 1 rd8-#xx:8-c rd8 [5] 1 rd8-rs8-c rd8 [5] 1 erd32-1 erd32 1 erd32-2 erd32 1 erd32-4 erd32 1 rd8-1 rd8 1 rd16-1 rd16 1 rd16-2 rd16 1 erd32-1 erd32 1 erd32-2 erd32 1 rd8 decimal adjust rd8 * * 1 rd8 rs8 rd16 (unsigned multiplication) 12 rd16 rs16 erd32 20 (unsigned multiplication) rd8 rs8 rd16 (signed multiplication) 13 rd16 rs16 erd32 21 (signed multiplication) operation condition code ihnzvc advanced no. of states * 1 ?? ?? ?????? ?????? ????? ??? ????? ????? ????? ?? 634 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic divxu divxs cmp neg extu divxu.b rs,rd b 2 divxu.w rs,erd w 2 divxs.b rs,rd b 4 divxs.w rs,erd w 4 cmp.b #xx:8,rd b 2 cmp.b rs,rd b 2 cmp.w #xx:16,rd w 4 cmp.w rs,rd w 2 cmp.l #xx:32,erd l 6 cmp.l ers,erd l 2 neg.b rd b 2 neg.w rd w 2 neg.l erd l 2 extu.w rd w 2 extu.l erd l 2 rd16 rs8 rd16 (rdh: remainder, [6] [7] 12 rdl: quotient) (unsigned division) erd32 rs16 erd32 (ed: remainder, [6] [7] 20 rd: quotient) (unsigned division) rd16 rs8 rd16 (rdh: remainder, [8] [7] 13 rdl: quotient) (signed division) erd32 rs16 erd32 (ed: remainder, [8] [7] 21 rd: quotient) (signed division) rd8-#xx:8 1 rd8-rs8 1 rd16-#xx:16 [3] 2 rd16-rs16 [3] 1 erd32-#xx:32 [4] 3 erd32-ers32 [4] 1 0-rd8 rd8 1 0-rd16 rd16 1 0-erd32 erd32 1 0 ( 635 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic exts tas mac clrmac ldmac stmac exts.w rd w 2 exts.l erd l 2 tas @erd * 2 b 4 mac @ern+, @erm+ clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd ( 636 table a-3 logical instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic and or xor not and.b #xx:8,rd b 2 and.b rs,rd b 2 and.w #xx:16,rd w 4 and.w rs,rd w 2 and.l #xx:32,erd l 6 and.l ers,erd l 4 or.b #xx:8,rd b 2 or.b rs,rd b 2 or.w #xx:16,rd w 4 or.w rs,rd w 2 or.l #xx:32,erd l 6 or.l ers,erd l 4 xor.b #xx:8,rd b 2 xor.b rs,rd b 2 xor.w #xx:16,rd w 4 xor.w rs,rd w 2 xor.l #xx:32,erd l 6 xor.l ers,erd l 4 not.b rd b 2 not.w rd w 2 not.l erd l 2 rd8 #xx:8 rd8 0 1 rd8 rs8 rd8 0 1 rd16 #xx:16 rd16 0 2 rd16 rs16 rd16 0 1 erd32 #xx:32 erd32 0 3 erd32 ers32 erd32 0 2 rd8 #xx:8 rd8 0 1 rd8 rs8 rd8 0 1 rd16 #xx:16 rd16 0 2 rd16 rs16 rd16 0 1 erd32 #xx:32 erd32 0 3 erd32 ers32 erd32 0 2 rd8 #xx:8 rd8 0 1 rd8 rs8 rd8 0 1 rd16 #xx:16 rd16 0 2 rd16 rs16 rd16 0 1 erd32 #xx:32 erd32 0 3 erd32 ers32 erd32 0 2 ? rd8 rd8 0 1 ? rd16 rd16 0 1 ? erd32 erd32 0 1 operation condition code ihnzvc advanced no. of states * 1 ????????????????????? ????????????????????? 637 table a-4 shift instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic shal shar shll shal.b rd b 2 shal.b #2,rd b 2 shal.w rd w 2 shal.w #2,rd w 2 shal.l erd l 2 shal.l #2,erd l 2 shar.b rd b 2 shar.b #2,rd b 2 shar.w rd w 2 shar.w #2,rd w 2 shar.l erd l 2 shar.l #2,erd l 2 shll.b rd b 2 shll.b #2,rd b 2 shll.w rd w 2 shll.w #2,rd w 2 shll.l erd l 2 shll.l #2,erd l 2 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ?????? ?????????????????? c msb lsb msb lsb 0 c msb lsb c 0 638 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic shlr rotxl rotxr shlr.b rd b 2 shlr.b #2,rd b 2 shlr.w rd w 2 shlr.w #2,rd w 2 shlr.l erd l 2 shlr.l #2,erd l 2 rotxl.b rd b 2 rotxl.b #2,rd b 2 rotxl.w rd w 2 rotxl.w #2,rd w 2 rotxl.l erd l 2 rotxl.l #2,erd l 2 rotxr.b rd b 2 rotxr.b #2,rd b 2 rotxr.w rd w 2 rotxr.w #2,rd w 2 rotxr.l erd l 2 rotxr.l #2,erd l 2 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ???????????? c msb lsb 0 c msb lsb c msb lsb 639 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic rotl rotr rotl.b rd b 2 rotl.b #2,rd b 2 rotl.w rd w 2 rotl.w #2,rd w 2 rotl.l erd l 2 rotl.l #2,erd l 2 rotr.b rd b 2 rotr.b #2,rd b 2 rotr.w rd w 2 rotr.w #2,rd w 2 rotr.l erd l 2 rotr.l #2,erd l 2 operation condition code ihnzvc advanced no. of states * 1 ???????????? ???????????? ???????????? c msb lsb c msb lsb 640 table a-5 bit-manipulation instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bset bclr bset #xx:3,rd b 2 bset #xx:3,@erd b 4 bset #xx:3,@aa:8 b 4 bset #xx:3,@aa:16 b 6 bset #xx:3,@aa:32 b 8 bset rn,rd b 2 bset rn,@erd b 4 bset rn,@aa:8 b 4 bset rn,@aa:16 b 6 bset rn,@aa:32 b 8 bclr #xx:3,rd b 2 bclr #xx:3,@erd b 4 bclr #xx:3,@aa:8 b 4 bclr #xx:3,@aa:16 b 6 bclr #xx:3,@aa:32 b 8 bclr rn,rd b 2 bclr rn,@erd b 4 bclr rn,@aa:8 b 4 bclr rn,@aa:16 b 6 (#xx:3 of rd8) 1 1 (#xx:3 of @erd) 1 4 (#xx:3 of @aa:8) 1 4 (#xx:3 of @aa:16) 1 5 (#xx:3 of @aa:32) 1 6 (rn8 of rd8) 1 1 (rn8 of @erd) 1 4 (rn8 of @aa:8) 1 4 (rn8 of @aa:16) 1 5 (rn8 of @aa:32) 1 6 (#xx:3 of rd8) 0 1 (#xx:3 of @erd) 0 4 (#xx:3 of @aa:8) 0 4 (#xx:3 of @aa:16) 0 5 (#xx:3 of @aa:32) 0 6 (rn8 of rd8) 0 1 (rn8 of @erd) 0 4 (rn8 of @aa:8) 0 4 (rn8 of @aa:16) 0 5 operation condition code ihnzvc advanced no. of states * 1 641 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bclr bnot btst bclr rn,@aa:32 b 8 bnot #xx:3,rd b 2 bnot #xx:3,@erd b 4 bnot #xx:3,@aa:8 b 4 bnot #xx:3,@aa:16 b 6 bnot #xx:3,@aa:32 b 8 bnot rn,rd b 2 bnot rn,@erd b 4 bnot rn,@aa:8 b 4 bnot rn,@aa:16 b 6 bnot rn,@aa:32 b 8 btst #xx:3,rd b 2 btst #xx:3,@erd b 4 btst #xx:3,@aa:8 b 4 btst #xx:3,@aa:16 b 6 (rn8 of @aa:32) 0 6 (#xx:3 of rd8) [? (#xx:3 of rd8)] 1 (#xx:3 of @erd) 4 [? (#xx:3 of @erd)] (#xx:3 of @aa:8) 4 [? (#xx:3 of @aa:8)] (#xx:3 of @aa:16) 5 [? (#xx:3 of @aa:16)] (#xx:3 of @aa:32) 6 [? (#xx:3 of @aa:32)] (rn8 of rd8) [? (rn8 of rd8)] 1 (rn8 of @erd) [? (rn8 of @erd)] 4 (rn8 of @aa:8) [? (rn8 of @aa:8)] 4 (rn8 of @aa:16) 5 [? (rn8 of @aa:16)] (rn8 of @aa:32) 6 [? (rn8 of @aa:32)] ? (#xx:3 of rd8) z 1 ? (#xx:3 of @erd) z 3 ? (#xx:3 of @aa:8) z 3 ? (#xx:3 of @aa:16) z 4 operation condition code ihnzvc advanced no. of states * 1 ???? 642 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic btst bld bild bst btst #xx:3,@aa:32 b 8 btst rn,rd b 2 btst rn,@erd b 4 btst rn,@aa:8 b 4 btst rn,@aa:16 b 6 btst rn,@aa:32 b 8 bld #xx:3,rd b 2 bld #xx:3,@erd b 4 bld #xx:3,@aa:8 b 4 bld #xx:3,@aa:16 b 6 bld #xx:3,@aa:32 b 8 bild #xx:3,rd b 2 bild #xx:3,@erd b 4 bild #xx:3,@aa:8 b 4 bild #xx:3,@aa:16 b 6 bild #xx:3,@aa:32 b 8 bst #xx:3,rd b 2 bst #xx:3,@erd b 4 bst #xx:3,@aa:8 b 4 ? (#xx:3 of @aa:32) z 5 ? (rn8 of rd8) z 1 ? (rn8 of @erd) z 3 ? (rn8 of @aa:8) z 3 ? (rn8 of @aa:16) z 4 ? (rn8 of @aa:32) z 5 (#xx:3 of rd8) c 1 (#xx:3 of @erd) c 3 (#xx:3 of @aa:8) c 3 (#xx:3 of @aa:16) c 4 (#xx:3 of @aa:32) c 5 ? (#xx:3 of rd8) c 1 ? (#xx:3 of @erd) c 3 ? (#xx:3 of @aa:8) c 3 ? (#xx:3 of @aa:16) c 4 ? (#xx:3 of @aa:32) c 5 c (#xx:3 of rd8) 1 c (#xx:3 of @erd) 4 c (#xx:3 of @aa:8) 4 operation condition code ihnzvc advanced no. of states * 1 ?????????? ?????? 643 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bst bist band biand bor bst #xx:3,@aa:16 b 6 bst #xx:3,@aa:32 b 8 bist #xx:3,rd b 2 bist #xx:3,@erd b 4 bist #xx:3,@aa:8 b 4 bist #xx:3,@aa:16 b 6 bist #xx:3,@aa:32 b 8 band #xx:3,rd b 2 band #xx:3,@erd b 4 band #xx:3,@aa:8 b 4 band #xx:3,@aa:16 b 6 band #xx:3,@aa:32 b 8 biand #xx:3,rd b 2 biand #xx:3,@erd b 4 biand #xx:3,@aa:8 b 4 biand #xx:3,@aa:16 b 6 biand #xx:3,@aa:32 b 8 bor #xx:3,rd b 2 bor #xx:3,@erd b 4 c (#xx:3 of @aa:16) 5 c (#xx:3 of @aa:32) 6 ? c (#xx:3 of rd8) 1 ? c (#xx:3 of @erd) 4 ? c (#xx:3 of @aa:8) 4 ? c (#xx:3 of @aa:16) 5 ? c (#xx:3 of @aa:32) 6 c (#xx:3 of rd8) c 1 c (#xx:3 of @erd) c 3 c (#xx:3 of @aa:8) c 3 c (#xx:3 of @aa:16) c 4 c (#xx:3 of @aa:32) c 5 c [? (#xx:3 of rd8)] c 1 c [? (#xx:3 of @erd)] c 3 c [? (#xx:3 of @aa:8)] c 3 c [? (#xx:3 of @aa:16)] c 4 c [? (#xx:3 of @aa:32)] c 5 c (#xx:3 of rd8) c 1 c (#xx:3 of @erd) c 3 operation condition code ihnzvc advanced no. of states * 1 ???????????? 644 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bor bior bxor bixor bor #xx:3,@aa:8 b 4 bor #xx:3,@aa:16 b 6 bor #xx:3,@aa:32 b 8 bior #xx:3,rd b 2 bior #xx:3,@erd b 4 bior #xx:3,@aa:8 b 4 bior #xx:3,@aa:16 b 6 bior #xx:3,@aa:32 b 8 bxor #xx:3,rd b 2 bxor #xx:3,@erd b 4 bxor #xx:3,@aa:8 b 4 bxor #xx:3,@aa:16 b 6 bxor #xx:3,@aa:32 b 8 bixor #xx:3,rd b 2 bixor #xx:3,@erd b 4 bixor #xx:3,@aa:8 b 4 bixor #xx:3,@aa:16 b 6 bixor #xx:3,@aa:32 b 8 c (#xx:3 of @aa:8) c 3 c (#xx:3 of @aa:16) c 4 c (#xx:3 of @aa:32) c 5 c [? (#xx:3 of rd8)] c 1 c [? (#xx:3 of @erd)] c 3 c [? (#xx:3 of @aa:8)] c 3 c [? (#xx:3 of @aa:16)] c 4 c [? (#xx:3 of @aa:32)] c 5 c (#xx:3 of rd8) c 1 c (#xx:3 of @erd) c 3 c (#xx:3 of @aa:8) c 3 c (#xx:3 of @aa:16) c 4 c (#xx:3 of @aa:32) c 5 c [? (#xx:3 of rd8)] c 1 c [? (#xx:3 of @erd)] c 3 c [? (#xx:3 of @aa:8)] c 3 c [? (#xx:3 of @aa:16)] c 4 c [? (#xx:3 of @aa:32)] c 5 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? 645 table a-6 branch instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bcc always 2 3 never 2 3 c z=0 2 3 c z=1 2 3 c=0 2 3 c=1 2 3 z=0 2 3 z=1 2 3 v=0 2 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bra d:8(bt d:8) 2 if condition is true then bra d:16(bt d:16) 4 pc pc+d brn d:8(bf d:8) 2 else next; brn d:16(bf d:16) 4 bhi d:8 2 bhi d:16 4 bls d:8 2 bls d:16 4 bcc d:b(bhs d:8) 2 bcc d:16(bhs d:16) 4 bcs d:8(blo d:8) 2 bcs d:16(blo d:16) 4 bne d:8 2 bne d:16 4 beq d:8 2 beq d:16 4 bvc d:8 2 bvc d:16 4 646 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic bcc v=1 2 3 n=0 2 3 n=1 2 3 n v=0 2 3 n v=1 2 3 z (n v)=0 2 3 z (n v)=1 2 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bvs d:8 2 bvs d:16 4 bpl d:8 2 bpl d:16 4 bmi d:8 2 bmi d:16 4 bge d:8 2 bge d:16 4 blt d:8 2 blt d:16 4 bgt d:8 2 bgt d:16 4 ble d:8 2 ble d:16 4 647 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic jmp bsr jsr rts jmp @ern 2 jmp @aa:24 4 jmp @@aa:8 2 bsr d:8 2 bsr d:16 4 jsr @ern 2 jsr @aa:24 4 jsr @@aa:8 2 rts 2 pc ern 2 pc aa:24 3 pc @aa:8 5 pc @-sp,pc pc+d:8 4 pc @-sp,pc pc+d:16 5 pc @-sp,pc ern 4 pc @-sp,pc aa:24 5 pc @-sp,pc @aa:8 6 pc @sp+ 5 operation condition code ihnzvc advanced no. of states * 1 648 table a-7 system control instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic trapa rte sleep ldc trapa #xx:2 rte sleep ldc #xx:8,ccr b 2 ldc #xx:8,exr b 4 ldc rs,ccr b 2 ldc rs,exr b 2 ldc @ers,ccr w 4 ldc @ers,exr w 4 ldc @(d:16,ers),ccr w 6 ldc @(d:16,ers),exr w 6 ldc @(d:32,ers),ccr w 10 ldc @(d:32,ers),exr w 10 ldc @ers+,ccr w 4 ldc @ers+,exr w 4 ldc @aa:16,ccr w 6 ldc @aa:16,exr w 6 ldc @aa:32,ccr w 8 ldc @aa:32,exr w 8 pc @-sp,ccr @-sp, 1 8 [9] exr @-sp, 649 addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic stc andc orc xorc nop stc ccr,rd b 2 stc exr,rd b 2 stc ccr,@erd w 4 stc exr,@erd w 4 stc ccr,@(d:16,erd) w 6 stc exr,@(d:16,erd) w 6 stc ccr,@(d:32,erd) w 10 stc exr,@(d:32,erd) w 10 stc ccr,@-erd w 4 stc exr,@-erd w 4 stc ccr,@aa:16 w 6 stc exr,@aa:16 w 6 stc ccr,@aa:32 w 8 stc exr,@aa:32 w 8 andc #xx:8,ccr b 2 andc #xx:8,exr b 4 orc #xx:8,ccr b 2 orc #xx:8,exr b 4 xorc #xx:8,ccr b 2 xorc #xx:8,exr b 4 nop 2 ccr rd8 1 exr rd8 1 ccr @erd 3 exr @erd 3 ccr @(d:16,erd) 4 exr @(d:16,erd) 4 ccr @(d:32,erd) 6 exr @(d:32,erd) 6 erd32-2 erd32,ccr @erd 4 erd32-2 erd32,exr @erd 4 ccr @aa:16 4 exr @aa:16 4 ccr @aa:32 5 exr @aa:32 5 ccr #xx:8 ccr 1 exr #xx:8 exr 2 ccr #xx:8 ccr 1 exr #xx:8 exr 2 ccr #xx:8 ccr 1 exr #xx:8 exr 2 pc pc+2 1 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 650 table a-8 block transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @Cern/@ern+ @aa @(d,pc) @@aa mnemonic eepmov notes: *1 the number of states is the number of states required for execution when the instruction and its operands are located in on-chi p memory. *2 this instruction should be used with the er0, er1, er4, or er5 general register only. *3 n is the initial value of r4l or r4. [1] seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] cannot be used in the h8s/2214. [3] set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] retains its previous value when the result is zero; otherwise cleared to 0. [6] set to 1 when the divisor is negative; otherwise cleared to 0. [7] set to 1 when the divisor is zero; otherwise cleared to 0. [8] set to 1 when the quotient is negative; otherwise cleared to 0. [9] one additional state is required for execution when exr is valid. eepmov.b 4 eepmov.w 4 if r4l 0 4+2n * 3 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4l-1 r4l until r4l=0 else next; if r4 0 4+2n * 3 repeat @er5 @er6 er5+1 er5 er6+1 er6 r4-1 r4 until r4=0 else next; operation condition code ihnzvc advanced no. of states * 1 651 a.2 instruction codes table a-9 shows the instruction codes. table a-9 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0 erd 0 imm 0 imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm 652 bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0 653 bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm 654 bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1 rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 655 bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs 656 btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b b b w w l l b b b w w l l b w b w 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0 erd 0 imm 0 imm 0 0 7 6 6 7 7 7 6 6 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm cannot be used in the h8s/2214 657 exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp abs abs disp disp 658 0 0 rd abs rs rd ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm ldmac mac mov w w l l l l l b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern+1 ern+2 ern+3 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 rs 0 2 8 a 0 rs 0 1 0 0 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 b b d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp cannot be used in the h8s/2214 659 mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * 1 mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs cannot be used in the h8s/2214 disp disp 660 neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm 661 rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd 662 shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp 663 stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd * 2 trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm stmac sub subs subx tas trapa xor w w w w l l l l l b w w l l l l l b b b b b w w l l 1 00 ers imm 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm cannot be used in the h8s/2214 664 xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm notes: *1 bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. *2 this instruction should be used with the er0, er1, er4, or er5 general register only. legend address register 32-bit register register field general register register field general register register field general register 000 001 ? ? ? 111 er0 er1 ? ? ? er7 0000 0001 ? ? ? 0111 1000 1001 ? ? ? 1111 r0 r1 ? ? ? r7 e0 e1 ? ? ? e7 0000 0001 ? ? ? 0111 1000 1001 ? ? ? 1111 r0h r1h ? ? ? r7h r0l r1l ? ? ? r7l 16-bit register 8-bit register imm: abs: d isp: rs, rd, rn: ers, erd, ern, erm: t he register fields specify general registers as follows. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn.) register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to oper and symbols ers, erd, ern, and erm.) 665 a.3operation code map tables a-10 to a-13 show the operation code map. instruction code 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah note: * cannot be used in the h8s/2214. al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3(2) table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.11 table a.12 table a-10 operation code map (1) ** 666 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe * or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe * d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al table a.12 table a.12 table a.12 table a.13 table a.13 * * note: * cannot be used in the h8s/2214. instruction code table a-11 operation code map (2) 667 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification field. aa is the absolute address specification. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef *1 *2 bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist table a-12 operation code map (3) 668 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef instruction code table a-13 operation code map (4) 669 a.4 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8s/2000 cpu. table a-15 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a-14 indicates the number of states required for each cycle, depending on its size. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffb3:8 from table a-15: i = l = 2, j = k = m = n = 0 from table a-14: s i = 4, s l = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table a-15: i = j = k = 2, l = m = n = 0 from table a-14: s i = s j = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24 670 table a-14 number of states per cycle access conditions on-chip supporting external device module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 2 2 3 + m word data access s m 4 4 6 + 2m internal operation s n 11 1 1111 legend m: number of wait states inserted into external device access 671 table a-15 number of cycles in instruction execution instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.w rs,rd 1 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2 672 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1 bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2 673 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1 bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1 674 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2 bsr bsr d:8 2 2 bsr d:16 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2 675 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac clrmac cannot be used in the h8s/2214 cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19 676 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n eepmov eepmov.b 2 2n+2* 2 eepmov.w 2 2n+2* 2 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 2 2 1 jsr jsr @ern 2 2 jsr @aa:24 2 2 1 jsr @@aa:8 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1 677 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n ldm ldm.l @sp+, (ern-ern+1) 24 1 ldm.l @sp+, (ern-ern+2) 26 1 ldm.l @sp+, (ern-ern+3) 28 1 ldmac ldmac ers,mach cannot be used in the h8s/2214 ldmac ers,macl mac mac @ern+,@erm+ cannot be used in the h8s/2214 mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@-erd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1 678 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@-erd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2 mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@-erd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 movfpe movfpe @:aa:16,rd can not be used in the h8s/2214 movtpe movtpe rs,@:aa:16 mulxs mulxs.b rs,rd 2 11 mulxs.w rs,erd 2 19 mulxu mulxu.b rs,rd 1 11 mulxu.w rs,erd 1 19 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1 679 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1 rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1 680 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3* 1 1 rts rts 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1 shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1 681 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@-erd 2 1 1 stc.w exr,@-erd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm stm.l (ern-ern+1), @-sp 24 1 stm.l (ern-ern+2), @-sp 26 1 stm.l (ern-ern+3), @-sp 28 1 stmac stmac mach,erd cannot be used in the h8s/2214 stmac macl,erd sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas tas @erd* 3 22 trapa trapa #x:2 2 2 2/3* 1 2 682 instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc #xx:8,exr 2 notes: *1 2 when exr is invalid, 3 when exr is valid. *2 when n bytes of data are transferred. *3 this instruction should be used with the er0, er1, er4, or er5 general register only. 683 a.5 bus states during instruction execution table a-16 indicates the types of cycles that occur during instruction execution by the cpu. see table a-14 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation 1 state r:w ea 1 2345678 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address 684 figure a-1 shows timing waveforms for the address bus and the rd , hwr , and lwr signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. ? address bus rd hwr , lwr r:w 2nd fetching 2nd byte of instruction at jump address fetching 1nd byte of instruction at jump address fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a-1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states) 685 instruction add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea 1 2 3 4 5 6 7 8 9 table a-16 instruction execution cycles 686 instruction ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea 1 2 3 4 5 6 7 8 9 687 instruction bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next 1 2 3 4 5 6 7 8 9 688 instruction bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w :m stack (h) w:w stack (l) bsr d:16 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next 1 2 3 4 5 6 7 8 9 689 instruction 1 2 3 4 5 6 7 8 9 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac cannot be used in the h8s/2214 cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next repeated n times * 2 exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next 690 instruction inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern r:w next r:w ea w:w :m stack (h) w:w stack (l) jsr @aa:24 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state jsr @@aa:8 r:w next r:w:m aa:8 r:w aa:8 w:w :m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 (ernCern+1) 1 state ldm.l @sp+,(ernCern+2) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ernCern+3) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach cannot be used in the h8s/2214 1 2 3 4 5 6 7 8 9 691 instruction ldmac ers,macl cannot be used in the h8s/2214 mac @ern+,@erm+ mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@Cerd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@Cerd r:w next internal operation, w:w ea 1 state mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea 1 2 3 4 5 6 7 8 9 692 instruction 1 2 3 4 5 6 7 8 9 mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@Cerd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in the h8s/2214 movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 11 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 19 states mulxu.b rs,rd r:w next internal operation, 11 states mulxu.w rs,erd r:w next internal operation, 19 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next 693 instruction pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 4 1 state rts r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 4 1 state shal.b rd r:w next 1 2 3 4 5 6 7 8 9 694 instruction shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation:m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state 1 2 3 4 5 6 7 8 9 695 instruction stc exr,@Cerd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ernCern+1),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ernCern+2),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ernCern+3),@Csp r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd cannot be used in the h8s/2214 stmac macl,erd sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd * 5 r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 8 1 state 1 state xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset exception r:w:m vec r:w vec+2 internal operation, r:w * 6 handling 1 state 1 2 3 4 5 6 7 8 9 696 instruction interrupt exception r:w * 7 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 8 handling 1 state 1 state notes: *1 eas is the contents of er5. ead is the contents of er6. *2 eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instruction. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. *3 repeated two times to save or restore two registers, three times for three registers, or four times for four registers. *4 start address after return. *5 this instruction should be used with the er0, er1, er4, or er5 general register only. *6 start address of the program. *7 prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mode th e read operation is replaced by an internal operation. *8 start address of the interrupt-handling routine. 1 2 3 4 5 6 7 8 9 697 a.6 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands si di ri dn 0 1 * z' c' the i-th bit of the source operand the i-th bit of the destination operand the i-th bit of the result the specified bit in the destination operand not affected modified according to the result of the instruction (see definition) always cleared to 0 always set to 1 undetermined (no guaranteed value) z flag before instruction execution c flag before instruction execution 698 table a-17 condition code modification instruction h n z v c definition add h = smC4 dmC4 + dmC4 rmC4 + smC4 rmC4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm adds addx h = smC4 dmC4 + dmC4 rmC4 + smC4 rmC4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm and 0 n = rm z = rm rmC1 ...... r0 andc stores the corresponding bits of the result. no flags change when the operand is exr. band c = c' dn bcc bclr biand c = c' dn bild c = dn bior c = c' + dn bist bixor c = c' dn + c' dn bld c = dn bnot bor c = c' + dn bset bsr bst btst z = dn bxor c = c' dn + c' dn clrmac cannot be used in the h8s/2214 699 instruction h n z v c definition cmp h = smC4 dmC4 + dmC4 rmC4 + smC4 rmC4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm daa * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic carry das * * n = rm z = rm rmC1 ...... r0 c: decimal arithmetic borrow dec n = rm z = rm rmC1 ...... r0 v = dm rm divxs n = sm dm + sm dm z = sm smC1 ...... s0 divxu n = sm z = sm smC1 ...... s0 eepmov exts 0 n = rm z = rm rmC1 ...... r0 extu 0 0 z = rm rmC1 ...... r0 inc n = rm z = rm rmC1 ...... r0 v = dm rm jmp jsr ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ldmac cannnot be used in the h8s/2214 mac 700 instruction h n z v c definition mov 0 n = rm z = rm rmC1 ...... r0 movfpe can not be used in the h8s/2214 movtpe mulxs n = r2m z = r2m r2mC1 ...... r0 mulxu neg h = dmC4 + rmC4 n = rm z = rm rmC1 ...... r0 v = dm rm c = dm + rm nop not 0 n = rm z = rm rmC1 ...... r0 or 0 n = rm z = rm rmC1 ...... r0 orc stores the corresponding bits of the result. no flags change when the operand is exr. pop 0 n = rm z = rm rmC1 ...... r0 push 0 n = rm z = rm rmC1 ...... r0 rotl 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotr 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) 701 instruction h n z v c definition rotxl 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) rotxr 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts shal n = rm z = rm rmC1 ...... r0 v = dm dmC1 + dm dmC1 (1-bit shift) v = dm dmC1 dmC2 dm dmC1 dmC2 (2-bit shift) c = dm (1-bit shift) or c = dmC1 (2-bit shift) shar 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) shll 0 n = rm z = rm rmC1 ...... r0 c = dm (1-bit shift) or c = dmC1 (2-bit shift) shlr 0 0 n = rm z = rm rmC1 ...... r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep stc stm stmac cannot be used in the h8s/2214 702 instruction h n z v c definition sub h = smC4 dmC4 + dmC4 rmC4 + smC4 rmC4 n = rm z = rm rmC1 ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm subs subx h = smC4 dmC4 + dmC4 rmC4 + smC4 rmC4 n = rm z = z' rm ...... r0 v = sm dm rm + sm dm rm c = sm dm + dm rm + sm rm tas * 0 n = dm z = dm dmC1 ...... d0 trapa xor 0 n = rm z = rm rmC1 ...... r0 xorc stores the corresponding bits of the result. no flags change when the operand is exr. note: * this instruction should be used with the er0, er1, er4, or er5 general register only. 703 appendix b internal i/o register b.1 addresses address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ebc0 to h'efbf mra mrb sar sm1 chne sm0 disel dm1 dm0 md1 md0 dts sz dtc 16/32 * bit dar cra crb h'fdac dadr0 d/a converter 8 bit h'fdae dacr daoe0 h'fde4 sbycr ssby sts2 sts1 sts0 ope power-down state 8 bit h'fde5 syscr intm1 intm0 nmieg mrese rame mcu 8 bit h'fde6 sckcr pstop sck2 sck1 sck0 clock pulse generator, power-down state 8 bit h'fde7 mdcr mds2 mds1 msd0 mcu, rom 8 bit h'fde8 h'fde9 mstpcra mstpcrb mstpa7 mstpb7 mstpa6 mstpb6 mstpa5 mstpb5 mstpa4 mstpb4 mstpa3 mstpb3 mstpa2 mstpb2 mstpa1 mstpb1 mstpa0 mstpb0 power-down state 8 bit h'fdea mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 note: * located in on-chip ram. the bus width is 32 bits when the dtc accesses this area as register information, and 16 bits otherwise. 704 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fdeb pfcr ae3ae2ae1ae0 bus controller 8 bit h'fdec lpwrcr rfcut stc1 stc0 clock pulse generator 8 bit h'fdf8 semr0 sse abcs acs2 acs1 acs0 sci0 8 bit h'fe12 h'fe13 iscrh iscrl irq7scb irq3scb irq7sca irq3sca irq6scb irq2scb irq6sca irq2sca irq5scb irq1scb irq5sca irq1sca irq4scb irq0scb irq4sca irq0sca interrupt controller 8 bit h'fe14 ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'fe15 isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f h'fe16 to h'fe1e dtcer dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 dtc 8 bit h'fe1f dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'fe30 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port 8 bit h'fe32 p3ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'fe36 p7ddr p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr h'fe39 paddr pa3ddr pa2ddr pa1ddr pa0ddr h'fe3a pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'fe3b pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'fe3c pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'fe3d peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'fe3e pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr h'fe3f pgddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr h'fe40 papcr pa3pcr pa2pcr pa1pcr pa0pcr h'fe41 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'fe42 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'fe43 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'fe44 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'fe46 p3odr p36odr p35odr p34odr p33odr p32odr p31odr p30odr h'fe47 paodr pa3odr pa2odr pa1odr pa0odr h'fe4a ipinsel0 p36 irq7e p47 irq6e p46 irq5e p44 irq4e p43 irq3e p42 irq2e p41 irq1e p40 irq0e h'fe4e opinsel p76 stpoe p75 msoe p74 dtcoe 705 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'feb0 tstr cst2 cst1 cst0 tpu 8 bit h'feb1 tsyr sync2 sync1 sync0 h'fec0 h'fec1 ipra iprb ipr6 ipr6 ipr5 ipr5 ipr4 ipr4 ipr2 ipr2 ipr1 ipr1 ipr0 ipr0 interrupt controller 8 bit h'fec2 iprc ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec3 iprd ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec5 iprf ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec6 iprg ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec9 iprj ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'feca iprk ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fecc iprm ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fed0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller 8 bit h'fed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'fed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 h'fed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 h'fed4 bcrh icis1 icis0 brstrm brsts1 brsts0 h'fed5 bcrl brle w aite h'fedb ramer rams ram2 ram1 ram0 flash h'fee0 mar0ah dmac 16 bit h'fee1 h'fee2 mar0al h'fee3 h'fee4 ioar0a h'fee5 h'fee6 etcr0a h'fee7 h'fee8 mar0bh h'fee9 h'feea mar0bl h'feeb h'feec ioar0b h'feed h'feee etcr0b h'feef h'fef0 mar1ah h'fef1 h'fef2 mar1al h'fef3 706 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fef4 ioar1a dmac 16 bit h'fef5 h'fef6 etcr1a h'fef7 h'fef8 mar1bh h'fef9 h'fefa mar1bl h'fefb h'fefc ioar1b h'fefd h'fefe etcr1b h'feff h'ff00 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port 8 bit h'ff02 p3dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr h'ff06 p7dr p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr h'ff09 padr pa3dr pa2dr pa1dr pa0dr h'ff0a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr h'ff0b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff0c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ff0d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ff0e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ff0f pgdr pg4dr pg3dr pg2dr pg1dr pg0dr h'ff10 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 8 bit h'ff11 tmdr0 bfb bfa md3 md2 md1 md0 h'ff12 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff13 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ff14 tier0 tciev tgied tgiec tgieb tgiea h'ff15 tsr0 tcfv tgfd tgfc tgfb tgfa h'ff16 tcnt0 16 bit h'ff17 h'ff18 tgr0a h'ff19 h'ff1a tgr0b h'ff1b h'ff1c tgr0c h'ff1d h'ff1e tgr0d h'ff1f 707 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff20 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 8 bit h'ff21 tmdr1 md3md2md1md0 h'ff22 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff24 tier1 tcieu tciev tgieb tgiea h'ff25 tsr1 tcfd tcfu tcfv tgfb tgfa h'ff26 tcnt1 16 bit h'ff27 h'ff28 tgr1a h'ff29 h'ff2a tgr1b h'ff2b h'ff30 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 8 bit h'ff31 tmdr2 md3md2md1md0 h'ff32 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff34 tier2 ttge tcieu tciev tgieb tgiea h'ff35 tsr2 tcfd tcfu tcfv tgfb tgfa h'ff36 tcnt2 16 bit h'ff37 h'ff38 tgr2a h'ff39 h'ff3a tgr2b h'ff3b h'ff60 dmawer we1bwe1awe0bwe0a dmac 8 h'ff61 dmatcr tee1 tee0 h'ff62 dmacr0a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 16 h'ff63 dmacr0b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff64 dmacr1a dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff65 dmacr1b dtsz dtid rpe dtdir dtf3 dtf2 dtf1 dtf0 h'ff66 dmabcrh fae1 fae0 dta1b dta1a dta0b dta0a h'ff67 dmabcrl dte1b dte1a dte0b dte0a dtie1b dtie1a dtie0b dtie0a h'ff74 h'ff74 (write) tcsr0 tcnt0 ovf wt/ it tme cks2 cks1 cks0 watchdog timer 0 16 bit h'ff75 (read) tcnt0 h'ff76 (write) rstcsr0 wovf rste rsts h'ff77 (read) rstcsr wovf rste rsts 708 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff78 h'ff79 h'ff7a smr0 brr0 scr0 c/ a tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci0 8 bit h'ff7b tdr0 h'ff7c ssr0 tdre rdrf orer fer per tend mpb mpbt h'ff7d rdr0 h'ff7e scmr0 sdirsinv h'ff80 h'ff81 h'ff82 smr1 brr1 scr1 c/ a tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci1 8 bit h'ff83 tdr1 h'ff84 ssr1 tdre rdrf orer fer per tend mpb mpbt h'ff85 rdr1 h'ff86 scmr1 sdirsinv h'ff88 h'ff89 h'ff8a smr2 brr2 scr2 c/ a tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci2 8 bit h'ff8b tdr2 h'ff8c ssr2 tdre rdrf orer fer per tend mpb mpbt h'ff8d rdr2 h'ff8e scmr2 sdirsinv h'ffb0 port1 p17 p16 p15 p14 p13 p12 p11 p10 port 8 bit h'ffb2 port3 p36 p35 p34 p33 p32 p31 p30 h'ffb3 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ffb6 port7 p77 p76 p75 p74 p73 p72 p71 p70 h'ffb8 port9 p96 h'ffb9 porta pa3pa2pa1pa0 h'ffba portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ffbb portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ffbc portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ffbd porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ffbe portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 h'ffbf portg pg4 pg3 pg2 pg1 pg0 709 b.2 functions mradtc mode register a h'ebc0 to h'efbf dtc 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dtc data transfer size 0 1 byte-size transfer word-size transfer 0 1 0 1 sar is fixed sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) sar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) dtc transfer mode select dtc mode destination address mode 1 and 0 source address mode 1 and 0 0 1 destination side is repeat area or block area source side is repeat area or block area 0 1 0 1 dar is fixed dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) dar is decremented after a transfer (by C1 when sz = 0; by C2 when sz = 1) 0 1 0 1 0 1 normal mode repeat mode block transfer mode 710 mrbdtc mode register b h'ebc0 to h'efbf dtc 7 chne 6 disel 5 4 3 0 2 1 bit initial value : : r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dtc interrupt select reserved only 0 should be written to these bits 0 1 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) after a data transfer ends, the cpu interrupt is enabled (the dtc does &)%/%%4$&%) =& /)=%%4&2 dtc chain transfer enable 0 1 end of dtc data transfer (activation waiting state) dtc chain transfer (new register information is read, then data is transferred) sardtc source address register h'ebc0 to h'efbf dtc 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- specifies transfer data source address dardtc destination address register h'ebc0 to h'efbf dtc 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- specifies transfer data destination address 711 cradtc transfer count register a h'ebc0 to h'efbf dtc 15 14 13 12 11109876543210 crah cral bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- specifies the number of dtc data transfers crbdtc transfer count register b h'ebc0 to h'efbf dtc 15 14 13 12 11109876543210 bit initial value : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : specifies the number of dtc block data transfers dadr0d/a data register 0 h'fdac d/a 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : stores data for d/a conversion 712 dacrd/a control register h'fdae d/a 7 0 r/w 6 daoe0 0 r/w 5 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : d/a output enable 0 reserved 0 1 analog output da0 is disabled only 0 should be written to this bit reserved only 0 should be written to this bit channel 0 d/a conversion is enabled; analog output da0 is enabled 713 sbycrstandby control register h'fde4 power-down state 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 2 0 1 0 bit initial value r/w standby timer select standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states standby time = 2048 states standby time = 16 states * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output port enable software standby transition to sleep mode after execution of sleep instruction transition to software standby mode after execution of sleep instruction note: * cannot be used in the f-ztat version. 0 1 0 1 in software standby mode, address bus and bus control signals are high-impedance in software standby mode, address bus and bus control signals retain their output state 714 syscrsystem control register h'fde5 mcu 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : ram enable 0 1 on-chip ram is disabled on-chip ram is enabled manual reset select bit 0 1 manual reset is disabled manual reset is enabled nmi interrupt input edge select 0 1 interrupt request generated at falling edge of nmi input interrupt request generated at rising edge of nmi input interrupt control mode select 0 1 0 1 0 1 interrupt control mode 0 interrupts controlled by i bit setting prohibited interrupt control mode 2 interrupts controlled by bits i2 to i0, and ipr setting prohibited reserved only 0 should be written to this bit 715 sckcrsystem clock control register h'fde6 clock pulse generator 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 r/w 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : ?clock output disable pstop 0 1 ? output fixed high ? output fixed high fixed high fixed high high impedance high impedance system clock select 2 to 0 0 1 0 1 0 1 0 1 0 1 0 1 bus master is in high-speed mode medium-speed clock is ?/2 medium-speed clock is ?/4 medium-speed clock is ?/8 medium-speed clock is ?/16 medium-speed clock is ?/32 high-speed mode, medium- speed mode sleep mode software standby mode hardware standby mode reserved only 0 should be written to this bit reserved only 0 should be written to this bit mdcrmode control register h'fde7 mcu 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r note: * determined by pins md 2 to md 0 . bit initial value r/w : : : these bits correspond to the mode pins (md2 to md0). when mdcr is read, the input levels at the mode pins (md2 to md0) are latched in bits mds2 to mds0. mode select 2 to 0 716 mstpcramodule stop control register a mstpcrbmodule stop control register b mstpcrcmodule stop control register c h'fde8 h'fde9 h'fdea power-down state 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w mstpcra 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w mstpcrc module stop 0 1 module stop mode is cleared module stop mode is set 717 pfcrpin function control register h'fdeb bus controller 7 0 0 r/w 6 0 0 r/w 5 0 0 r/w 4 0 0 r/w 3 ae3 1 0 r/w 0 ae0 1 0 r/w 2 ae2 1 0 r/w 1 ae1 0 0 r/w bit modes 4 and 5 initial value modes 6 and 7 initial value r/w address output enable 3 to 0 a8 to a23 output disabled a8 output enabled; a9 to a23 output disabled a8, a9 output enabled; a10 to a23 output disabled a8 to a10 output enabled; a11 to a23 output disabled a8 to a11 output enabled; a12 to a23 output disabled a8 to a12 output enabled; a13 to a23 output disabled a8 to a13 output enabled; a14 to a23 output disabled a8 to a14 output enabled; a15 to a23 output disabled a8 to a15 output enabled; a16 to a23 output disabled a8 to a16 output enabled; a17 to a23 output disabled a8 to a17 output enabled; a18 to a23 output disabled a8 to a18 output enabled; a19 to a23 output disabled a8 to a19 output enabled; a20 to a23 output disabled a8 to a20 output enabled; a21 to a23 output disabled a8 to a21 output enabled; a22, a23 output disabled a8 to a23 output enabled 0 1 note: in expanded mode with on-chip rom enabled, address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1; in expanded mode with on-chip rom disabled, address pins a0 to a7 are always address outputs. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 reserved only 0 should be written to these bits 718 lpwrcrlow-power control register h'fdec power-down state 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 0 r/w 1 stc1 0 r/w bit initial value r/w reserved only 0 should be written to this bit reserved only 0 should be written to these bits built-in feedback resistor control 0 1 system clock oscillator's built-in feedback resistor and duty adjustment circuit are used system clock oscillator's built-in feedback resistor and duty adjustment circuit are not used frequency multiplication factor 0 1 0 1 0 1 x1 (initial value) x2 (setting prohibited) x4 (setting prohibited) pll is bypassed 719 semr0serial extended mode register 0 h'fdf8 sci0 7 sse 0 r/w 6 unde- fined 5 unde- fined 4 unde- fined 3 abcs 0 r/w 0 acs0 0 r/w 2 acs2 0 r/w 1 acs1 0 r/w bit initial value r/w asynchronous base clock select sci0 select enable sci0 select function disabled sci0 select function enabled when pg1/irq7 pin input = 1, txd0 goes to high-impedance state and sck0 clock input is fixed high 0 1 0 1 sci0 operates on base clock with frequency of 16 times transfer rate sci0 operates on base clock with frequency of 8 times transfer rate asynchronous clock source select 2 to 0 external clock input 115.152 kbps average transfer rate (for ? = 10.667 mhz only) is selected (sci0 operates on base clock with frequency of 16 times transfer rate) 460.606 kbps average transfer rate (for ? = 10.667 mhz only) is selected (sci0 operates on base clock with frequency of 8 times transfer rate) reserved tpu clock input (and of tioca1 and tioca2) 115.196 kbps average transfer rate (for ? = 16 mhz only) $$) +7&4%$&,$)&)5./ %e)# of 16 times transfer rate) 460.784 kbps average transfer rate (for ? = 16 mhz only) $$) +7&4%$&,$)&)5./ %e)# of 16 times transfer rate) 720 kbps average transfer rate (for ? = 16 mhz only) is selected (sci0 operates on base clock with frequency of 8 times transfer rate) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 reserved bits write 0 to these bits 720 iscrhirq sense control register h iscrlirq sense control register l h'fe12 h'fe13 interrupt controller interrupt controller 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : irq7 to irq4 sense control a and b iscrh iscrl irq3 to irq0 sense control a and b irqnscb 0 1 (n = 7 to 0) irqnsca 0 1 0 1 interrupt request generation irqn input low level falling edge of irqn input rising edge of irqn input both falling and rising edges of irqn input 721 ierirq enable register h'fe14 interrupt controller 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : irqn enable 0 1 irqn interrupts disabled irqn interrupts enabled (n = 7 to 0) isrirq status register h'fe15 interrupt controller 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * only 0 can be written, to clear the flag. : : : indicates the status of irqn interrupt requests 1 2 [clearing conditions] (initial value) ? cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag ? when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high ? when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) ? when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 [setting conditions] ? when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) ? when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) ? when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) ? when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 7 to 0) 722 dtcerdtc enable registers h'fe16 to h'fe1e dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : dtc activation enable 0 1 dtc activation by this interrupt is disabled [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended dtvecrdtc vector register h'fe1f dtc 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 notes: *1 only 1 can be written to the swdte bit. *2 bits dtvec6 to dtvec0 can be written to when swdte = 0. bit initial value r/w : : : dtc software activation enable sets vector number for dtc software activation 0 1 dtc software activation is disabled [clearing conditions] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 is written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation 723 p1ddrport 1 data direction register h'fe30 port 1 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value r/w specify input or output for the pins of port 1 p3ddrport 3 data direction register h'fe32 port 3 7 undefined 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value r/w specify input or output for the pins of port 3 p7ddrport 7 data direction register h'fe36 port 7 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 0 p70ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w bit initial value r/w specify input or output for the pins of port 7 paddrport a data direction register h'fe39 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value r/w specify input or output for the pins of port a 724 pbddrport b data direction register h'fe3a port b 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value r/w specify input or output for the pins of port b pcddrport c data direction register h'fe3b port c 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value r/w specify input or output for the pins of port c pdddrport d data direction register h'fe3c port d 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value r/w specify input or output for the pins of port d peddrport e data direction register h'fe3d port e 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value r/w specify input or output for the pins of port e 725 pfddrport f data direction register h'fe3e port f 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit modes 4 to 6 initial value r/w mode 7 initial value r/w specify input or output for the pins of port f pgddrport g data direction register h'fe3f port g 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit modes 4 and 5 initial value r/w modes 6 and 7 initial value r/w specify input or output for the pins of port g 726 papcrport a mos pull-up control register h'fe40 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value r/w controls the mos input pull-up function incorporated into port a on a bit-by-bit basis pbpcrport b mos pull-up control register h'fe41 port b 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value r/w controls the mos input pull-up function incorporated into port b on a bit-by-bit basis pcpcrport c mos pull-up control register h'fe42 port c 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value r/w controls the mos input pull-up function incorporated into port c on a bit-by-bit basis pdpcrport d mos pull-up control register h'fe43 port d 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value r/w controls the mos input pull-up function incorporated into port d on a bit-by-bit basis 727 pepcrport e mos pull-up control register h'fe44 port e 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value r/w controls the mos input pull-up function incorporated into port e on a bit-by-bit basis p3odrport 3 open-drain control register h'fe46 port 3 7 undefined 6 p36odr 0 r/w 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value r/w controls the pmos on/off status for each port 3 pin (p36 to p30) paodrport a open-drain control register h'fe47 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value r/w controls the pmos on/off status for each port a pin (pa3 to pa0) 728 ipinsel0interrupt request input pin select register 0 h'fe4a bus controller ports q li q p 7 i wq i p 7 x wi x p 7 w ww w p 7 l wl l p 7 p wp p p 7 9 w9 9 p 7 8 w8 8 p 7 l l 7 v v v enable of exirq1 input from p41 (p41irq1e) enable of exirq0 input from p40 (p40irq0e) 0 1 p41 is not used as exirq1 exirq1 enable of exirq2 input from p42 (p42irq2e) 0 1 p42 is not used as exirq2 exirq2 enable of exirq3 input from p43 (p43irq3e) 0 1 p43 is not used as exirq3 exirq3 enable of exirq4 input from p44 (p44irq4e) 0 1 p44 is not used as exirq4 exirq4 enable of exirq5 input from p46 (p46irq5e) 0 1 p46 is not used as exirq5 exirq5 enable of exirq6 input from p47 (p47irq6e) 0 1 p47 is not used as exirq6 exirq6 enable of exirq7 input from p36 (p36irq7e) 0 1 p36 is not used as exirq7 exirq7 exirq0 exirq0 729 opinselexternal module connection output pin select register h'fe4e bus controller ports 7 undefined 6 p76 stope 0 r/w 5 p75 mse 0 r/w 4 p74 dtcoe 0 r/w 3 undefined 0 undefined 2 undefined 1 undefined bit initial value r/w : : : reserved bits enable of exdtce output to p74 (p74dtcoe) 0 1 exdtce is not output to p74 exdtce is output to p74 enable of exms output to p75 (p75msoe) 0 1 exms is not output to p75 exms is output to p75 enable of exmstp output to p76 (p76stpoe) 0 1 exmstp is not output to p76 exmstp is output to p76 reserved bit write 0 to this bit write 0 to these bits 730 tstrtimer start register h'feb0 tpu 7 0 6 0 5 0 4 0 3 0 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value r/w : : : counter start 2 to 0 0 1 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. tcntn count operation is stopped tcntn performs count operation (n = 2 to 0) tsyrtimer synchro register h'feb1 tpu 7 0 6 0 5 0 4 0 3 0 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w notes: to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 1. 2. : : : timer synchro 0 1 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible (n = 2 to 0) 731 ipra interrupt priority register a iprb interrupt priority register b iprc interrupt priority register c iprd interrupt priority register d iprf interrupt priority register f iprg interrupt priority register g iprj interrupt priority register j iprk interrupt priority register k iprm interrupt priority register m h'fec0 h'fec1 h'fec2 h'fec3 h'fec5 h'fec6 h'fec9 h'feca h'fecc interrupt controller 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w correspondence between interrupt sources and ipr settings note: * reserved bits. these bits cannot be modified and are always read as 1. : : : set priority (levels 7 to 0) for interrupt sources bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2, irq3 irq4, irq5 iprc irq6, irq7 dtc iprd watchdog timer 0 * iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 iprj dmac sci channel 0 iprk sci channel 1 sci channel 2 iprm exirq3 to exirq0 exirq7 to exirq4 732 abwcrbus width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : r/w initial value : : r/w area 7 to 0 bus width control 0 1 area n is designated for 16-bit access area n is designated for 8-bit access (n = 7 to 0) astcraccess state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : area 7 to 0 access state control 0 1 area n is designated for 2-state access wait state insertion in area n external space is disabled area n is designated for 3-state access wait state insertion in area n external space is enabled (n = 7 to 0) 733 wcrhwait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : area 7 wait control 1 and 0 area 4 wait control 1 and 0 program wait not inserted in area 4 external space access 1 program wait state inserted in area 4 external space access 2 program wait states inserted in area 4 external space access 3 program wait states inserted in area 4 external space access 0 1 0 1 0 1 program wait not inserted in area 5 external space access 1 program wait state inserted in area 5 external space access 2 program wait states inserted in area 5 external space access 3 program wait states inserted in area 5 external space access 0 1 0 1 0 1 program wait not inserted in area 6 external space access 1 program wait state inserted in area 6 external space access 2 program wait states inserted in area 6 external space access 3 program wait states inserted in area 6 external space access 0 1 0 1 0 1 program wait not inserted in area 7 external space access 1 program wait state inserted in area 7 external space access 2 program wait states inserted in area 7 external space access 3 program wait states inserted in area 7 external space access 0 1 0 1 0 1 area 5 wait control 1 and 0 area 6 wait control 1 and 0 734 wcrlwait control register l h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : area 3 wait control 1 and 0 area 0 wait control 1 and 0 program wait not inserted in area 0 external space access 1 program wait state inserted in area 0 external space access 2 program wait states inserted in area 0 external space access 3 program wait states inserted in area 0 external space access 0 1 0 1 0 1 program wait not inserted in area 1 external space access 1 program wait state inserted in area 1 external space access 2 program wait states inserted in area 1 external space access 3 program wait states inserted in area 1 external space access 0 1 0 1 0 1 program wait not inserted in area 2 external space access 1 program wait state inserted in area 2 external space access 2 program wait states inserted in area 2 external space access 3 program wait states inserted in area 2 external space access 0 1 0 1 0 1 program wait not inserted in area 3 external space access 1 program wait state inserted in area 3 external space access 2 program wait states inserted in area 3 external space access 3 program wait states inserted in area 3 external space access 0 1 0 1 0 1 area 1 wait control 1 and 0 area 2 wait control 1 and 0 735 bcrhbus control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : reserved only 0 should be written to these bits burst cycle select 0 0 1 max. 4 words in burst access max. 8 words in burst access burst cycle select 1 0 1 burst cycle comprises 1 state burst cycle comprises 2 states area 0 burst rom enable 0 1 area 0 is basic bus interface area 0 is burst rom interface idle cycle insert 0 0 1 idle cycle not inserted in case of successive external read and external write cycles idle cycle inserted in case of successive external read and external write cycles idle cycle insert 1 0 1 idle cycle not inserted in case of successive external read cycles in different areas idle cycle inserted in case of successive external read cycles in different areas 736 bcrlbus control register l h'fed5 bus controller q p 7 i p 7 x p w p 7 l 8 7 p p 7 9 p 7 8 p 7 l l 7 v v v wait pin enable reserved only 0 should be written to these bits reserved only 1 should be written to this bit reserved only 0 should be written to this bit reserved only 0 should be written to this bit 0 1 wait input by wait wait wait bus release enable 0 1 external bus release is disabled. breq back 737 ramerram emulation register h'fedb flash 7 0 r 6 0 r 5 0 r 4 0 r/w 3 rams 0 r/w 0 ram0 0 r/w 2 ram2 0 r/w 1 ram1 0 r/w bit initial value r/w : : : emulation not selected program/erase-protection of all flash memory blocks is disabled emulation selected program/erase-protection of all flash memory blocks is enabled 0 1 ram select flash memory area selection mar0amemory address register 0a h'fee0 dmac 16 * r/w 18 * r/w 17 * r/w 19 * r/w 21 * r/w 22 * r/w 23 * r/w 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w 20 * r/w * : undefined bit initial value r/w : : : bit initial value r/w : : : ioar0ai/o address register 0a h'fee4 dmac 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w * : undefined bit initial value r/w : : : 738 etcr0atransfer count register 0a h'fee6 dmac 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w * : undefined bit initial value r/w : : : etcr0btransfer count register 0b h'feee dmac 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w * : undefined bit initial value r/w : : : mar1amemory address register 1a h'fef0 dmac 16 * r/w 18 * r/w 17 * r/w 19 * r/w 21 * r/w 22 * r/w 23 * r/w 24 0 25 0 26 0 27 0 28 0 29 0 30 0 31 0 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w 20 * r/w * : undefined bit initial value r/w : : : bit initial value r/w : : : ioar1ai/o address register 1a h'fef4 dmac 0 * r/w 2 * r/w 1 * r/w 3 * r/w 4 * r/w 5 * r/w 6 * r/w 7 * r/w 8 * r/w 9 * r/w 10 * r/w 11 * r/w 12 * r/w 13 * r/w 14 * r/w 15 * r/w * : undefined bit initial value r/w : : : 739 etcr1atransfer count register 1a h'fef6 dmac 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 8 * r/w 10 * r/w 9 * r/w maintenance of transfer count transfer counter 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 0 * r/w 2 * r/w 1 * r/w * : undefined bit etcrl initial value r/w : : : : bit etcrh initial value r/w : : : : etcr1btransfer count register 1b h'fefe dmac 15 * r/w 14 * r/w 13 * r/w 12 * r/w 11 * r/w 8 * r/w 10 * r/w 9 * r/w maintenance of transfer count transfer counter 7 * r/w 6 * r/w 5 * r/w 4 * r/w 3 * r/w 0 * r/w 2 * r/w 1 * r/w * : undefined bit etcrl initial value r/w : : : : bit etcrh initial value r/w : : : : 740 p1drport 1 data register h'ff00 port 1 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value r/w : : : stores output data for the port 1 pins (p17 to p10) p3drport 3 data register h'ff02 port 3 7 undefined 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value r/w : : : stores output data for the port 3 pins (p36 to p30) p7drport 7 data register h'ff06 port 7 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 0 p70dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w bit initial value r/w : : : stores output data for the port 7 pins (p77 to p70) padrport a data register h'ff09 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value r/w : : : stores output data for the port a pins (pa3 to pa0) 741 pbdrport b data register h'ff0a port b 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value r/w : : : stores output data for the port b pins (pb7 to pb0) pcdrport c data register h'ff0b port c 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value r/w : : : stores output data for the port c pins (pc7 to pc0) pddrport d data register h'ff0c port d 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value r/w : : : stores output data for the port d pins (pd7 to pd0) pedrport e data register h'ff0d port e 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value r/w : : : stores output data for the port e pins (pe7 to pe0) 742 pfdrport f data register h'ff0e port f 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit initial value r/w : : : stores output data for the port f pins (pf7 to pf0) pgdrport g data register h'ff0f port g 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit initial value r/w : : : stores output data for the port g pins (pg4 to pg0) 743 tcr0timer control register 0 h'ff10 tpu0 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : counter clear 2 to 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 0 1 notes: *1 synchronous operation setting is performed by setting the sync bit in tsyr to 1. *2 when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 0 1 0 1 0 1 0 1 0 1 0 1 clock edge 1 and 0 0 1 0 1 count at rising edge count at falling edge count at both edges time prescaler 2 to 0 internal clock: counts on ?/1 internal clock: counts on ?/4 internal clock: counts on ?/16 internal clock: counts on ?/64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input external clock: counts on tclkd pin input 0 1 0 1 0 1 0 1 0 1 0 1 0 1 744 tmdr0timer mode register 0 h'ff11 tpu0 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : buffer operation a 0 1 tgra operates normally tgra and tgrc used together for buffer operation modes 3 to 0 normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 0 1 * : dont care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channel 0. in this case, 0 should always be written to md2. 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * buffer operation b 0 1 tgrb operates normally tgrb and tgrd used together for buffer operation 745 tior0htimer i/o control register 0h h'ff12 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. i/o control a3 to a0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca0 pin setting prohibited tgr0a is output compare register tgr0a is input capture register i/o control b3 to b0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb0 pin setting prohibited tgr0b is output compare register tgr0b is input capture register 746 tior0ltimer i/o control register 0l h'ff13 tpu0 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w note: *1 when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. bit initial value r/w : : : note: *1 when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer " #% "2,%% #% $$+ !+ " ) + !)*+" %) generated. i/o control c3 to c0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocc0 pin setting prohibited tgr0c is output compare register * 1 tgr0c is input capture register * 1 i/o control d3 to d0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd0 pin setting prohibited tgr0d is output compare register * 1 tgr0d is input capture register * 1 note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 747 tier0timer interrupt enable register 0 h'ff14 tpu0 7 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled tgr interrupt enable c 0 1 interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled tgr interrupt enable d 0 1 interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled reserved only 0 should be written to this bit 748 tsr0timer status register 0 h'ff15 tpu0 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value r/w note: * can only be written with 0 for flag clearing. : : : overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) input capture/output compare flag a 0 1 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when dmac is activated by tgia interrupt while dta bit of dmabcr in dmac is 1 ? when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register input capture/output compare flag c 0 1 [clearing conditions] ? when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfc after reading tgfc = 1 [setting conditions] ? when tcnt = tgrc while tgrc is functioning as output compare register ? when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register input capture/output compare flag d 0 1 [clearing conditions] ? when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfd after reading tgfd = 1 [setting conditions] ? when tcnt = tgrd while tgrd is functioning as output compare register ? when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register 749 tcnt0timer counter 0 h'ff16 tpu0 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w up-counter tgr0atimer general register 0a tgr0btimer general register 0b tgr0ctimer general register 0c tgr0dtimer general register 0d h'ff18 h'ff1a h'ff1c h'ff1e tpu0 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w 750 tcr1timer control register 1 h'ff20 tpu1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler 2 to 0 internal clock: counts on ?/1 internal clock: counts on ?/4 internal clock: counts on ?/16 internal clock: counts on ?/64 external clock: counts on tclka pin input external clock: counts on tclkb pin input internal clock: counts on ?/256 setting prohibited 0 1 note: this setting is ignored when channel 1 is in phase !) #*)$ 1 1 0 1 0 1 0 1 0 1 0 1 clock edge 1 and 0 count at rising edge count at falling edge count at both edges 0 1 note: * the internal clock edge selection is valid when the input clock is ?/4 or slower. this setting is ignored if the input clock is ?/1, or when overflow/underflow of another channel is selected. 0 1 * counter clear 2 to 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 2 0 1 0 * 1 notes: bit 7 is reserved. it cannot be modified and is always read as 0. synchronous operation setting is performed by setting the sync bit in tsyr to 1. *1 *2 0 1 0 1 751 tmdr1timer mode register 1 h'ff21 tpu1 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it should always be written with 0. * : dont care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 752 tior1timer i/o control register 1 h'ff22 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : i/o control a3 to a0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca1 pin setting prohibited tgr1a is output compare register tgr1a is input capture register 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb1 pin setting prohibited tgr1b is output compare register tgr1b is input capture register i/o control b3 to b0 753 tier1timer interrupt enable register 1 h'ff24 tpu1 7 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled reserved only 0 should be written to this bit 754 tsr1timer status register 1 h'ff25 tpu1 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: * can only be written with 0 for flag clearing. input capture/output compare flag a 0 1 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when dmac is activated by tgia interrupt while dta bit of dmabcr in dmac is 1 ? when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register f , %"%- "" $)(&'+ !+ " %# while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up 755 tcnt1timer counter 1 h'ff26 tpu1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : * these counters can be used as up/down-counters only in phase counting mode. in other cases they function as up-counters. up/down-counter * tgr1atimer general register 1a tgr1btimer general register 1b h'ff28 h'ff2a tpu1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w 756 tcr2timer control register 2 h'ff30 tpu2 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler 2 to 0 internal clock: counts on ?/1 internal clock: counts on ?/4 internal clock: counts on ?/16 internal clock: counts on ?/64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input internal clock: counts on ?/1024 0 1 note: this setting is ignored when channel 2 is in phase counting mode. 0 1 0 1 0 1 0 1 0 1 0 1 clock edge 1 and 0 count at rising edge count at falling edge count at both edges 0 1 note: the internal clock edge selection is valid when the input clock is ?/4 or slower. this setting is ignored if the input clock is ?/1, or when overflow/underflow of another channel is selected. 0 1 counter clear 2 to 0 tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 2 0 1 0 * 1 notes: *1 *2 bit 7 is reserved. it cannot be modified and is alway read as 0. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 0 1 0 1 757 tmdr2timer mode register 2 h'ff31 tpu2 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it %,) $:'%& :" :,1 * : dont care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 758 tior2timer i/o control register 2 h'ff32 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : i/o control a3 to a0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match + !+ " "%# $# input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca2 pin tgr2a is output compare register tgr2a is input capture register i/o control b3 to b0 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : dont care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb2 pin tgr2b is output compare register tgr2b is input capture register 759 tier2timer interrupt enable register 2 h'ff34 tpu2 7 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled reserved only 0 should be written to this bit 760 tsr2timer status register 2 h'ff35 tpu2 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: * can only be written with 0 for flag clearing. input capture/output compare flag a 0 1 [clearing conditions] ? when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ? when dmac is activated by tgia interrupt while dta bit of dmabcr in dmac is 1 ? when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ? when tcnt = tgra while tgra is functioning as output compare register ? when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ? when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ? when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ? when tcnt = tgrb while tgrb is functioning as output compare register ? when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up 761 tcnt2timer counter 2 h'ff36 tpu2 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : * these counters can be used as up/down-counters only in phase counting mode. in other cases they function as up-counters. up/down-counter * tgr2atimer general register 2a tgr2btimer general register 2b h'ff38 h'ff3a tpu2 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w 762 dmawerdma write enable register h'ff60 dmac 7 0 6 0 5 0 4 0 3 we1b 0 r/w 0 we0a 0 r/w 2 we1a 0 r/w 1 we0b 0 r/w write enable 1a disables writing to all dmacr1b bits, dmabcr bits 11, 7, and 3, and dmatcr bit 5. enables writing to all dmacr1b bits, dmabcr bits 11, 7, and 3, and dmatcr bit 5. 0 1 disables writing to all dmacr1a bits, and dmabcr bits 10, 6, and 2. enables writing to all dmacr1a bits, and dmabcr bits 10, 6, and 2. 0 1 disables writing to all dmacr0a bits, and dmabcr bits 8, 4, and 0. enables writing to all dmacr0a bits, and dmabcr bits 8, 4, and 0. 0 1 write enable 0b disables writing to all dmacr0b bits, dmabcr bits 9, 5, and 1, and dmatcr bit 4. enables writing to all dmacr0b bits, dmabcr bits 9, 5, and 1, and dmatcr bit 4. 0 1 write enable 0a write enable 1b bit initial value r/w : : : dmatcrdma terminal control register h'ff61 dmac 7 7 v ( 7 w c 7 7 w 9 7 7 7 ) 7 ( 7 e w e tend1 tend1 tend0 tend0 763 dmacr0adma control register 0a dmacr0bdma control register 0a dmacr1adma control register 1a dmacr1bdma control register 1b h'ff62 h'ff63 h'ff64 h'ff65 dmac dmac dmac dmac 7 dtsz 0 r/w 6 dtid 0 r/w 5 rpe 0 r/w 4 dtdir 0 r/w 3 dtf3 0 r/w 0 dtf0 0 r/w 2 dtf2 0 r/w 1 dtf1 0 r/w byte size transfer word size transfer 0 1 0 data transfer size mar incremented after data transfer (1) when dtsz=0, mar + 1 after transfer. (2) when dtsz=1, mar + 2 after transfer. mar decremented after data transfer (1) when dtsz=0, mar C 1 after transfer. (2) when dtsz=1, mar C 2 after transfer. 1 data transfer increment/decrement repeat enable data transfer direction data transfer factor channel a channel b sequential mode transfer (no transfer end interrrupt). sequential mode transfer (with transfer end interrupt). transfer in repeat mode (no transfer end interrupt). transfer in idle mode (with transfer end interrupt). 0 1 0 dtie dmabcr rpe 0 1 1 transfer from mar as source address to ioar as destination address. transfer from ioar as source address to mar as destination address. transfer from mar as source address with dack pin as write strobe. transfer with dack pin as read strobe to mar as destination address. 0 1 0 dtdir dmabcr sae 0 1 1 0 1 0 0 0 1 1 starts on sci channel 0 transmit end interrupt starts on sci channel 0 receive end interrupt starts on sci channel 1 transmit end interrupt starts on sci channel 1 receive end interrupt starts on tpu channel 0 compare match/input capture a interrupt starts on tpu channel 1 compare match/input capture a interrupt starts on tpu channel 2 compare match/input capture a interrupt 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 1 starts on falling edge of input at dreq pin starts on low level input at dreq pin starts on sci channel 0 transmit end interrupt starts on sci channel 0 receive end interrupt starts on sci channel 1 transmit end interrupt starts on sci channel 1 receive end interrupt starts on tpu channel 0 compare match/input capture a interrupt starts on tpu channel 1 compare match/input capture a interrupt starts on tpu channel 2 compare match/input capture a interrupt 0 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 1 0 1 1 note: * detect the first transfer after transfers have been enabled as a low level signal. bit dmacr initial value r/w : : : : 764 dmabcrdma band control register h'ff66 dmac 15 fae1 0 r/w 14 fae0 0 r/w 13 0 r/w * 12 0 r/w * 11 dta1b 0 r/w 8 dta0a 0 r/w 10 dta1a 0 r/w 9 dta0b 0 r/w full address enable 1 data transfer acknowledge 0a short address mode. full address mode. 0 1 short address mode. full address mode. 0 1 clearing of selected internal interrupt factor at dma transfer disabled. clearing of selected internal interrupt factor at dma transfer enabled. 0 1 clearing of selected internal interrupt factor at dma transfer disabled. clearing of selected internal interrupt factor at dma transfer enabled. 0 1 clearing of selected internal interrupt factor at dma transfer disabled. clearing of selected internal interrupt factor at dma transfer enabled. 0 1 clearing of selected internal interrupt factor at dma transfer disabled. clearing of selected internal interrupt factor at dma transfer enabled. 0 1 full address enable 0 data transfer acknowledge 0b data transfer acknowledge 1a data transfer acknowledge 1b bit dmabcrh initial value r/w : : : : note: * only 0 can be written to, writing 1 causes a malfunction error. 765 7 dte1b 0 r/w 6 dte1a 0 r/w 5 dte0b 0 r/w 4 dte0a 0 r/w 3 dtie1b 0 r/w 0 dtie0a 0 r/w 2 dtie1a 0 r/w 1 dtie0b 0 r/w data transfer enable 1b data transfer interrupt enable 0a data transfer disabled. data transfer enabled. 0 1 data transfer disabled. data transfer enabled. 0 1 data transfer disabled. data transfer enabled. 0 1 transfer end interrupt disabled. transfer end interrupt enabled. 0 1 transfer end interrupt disabled. transfer end interrupt enabled. 0 1 transfer end interrupt disabled. transfer end interrupt enabled. 0 1 transfer end interrupt disabled. transfer end interrupt enabled. 0 1 data transfer enable 1a data transfer disabled. data transfer enabled. 0 1 data transfer enable 0b data transfer enable 0a data transfer interrupt enable 0b data transfer interrupt enable 1a data transfer interrupt enable 1b bit dmabcrl initial value r/w : : : : 766 tcsr0timer control/status register h'ff74(w) h'ff74(r) wdt0 7 wn6 g w it 767 tcnt0timer counter h'ff74(w) h'ff75(r) wdt0 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : rstcsrreset control/status register h'ff76(w) h'ff77(r) wdt0 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : note: * only 0 can be written, to clear the flag. rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 11.2.4, notes on register access. reset select 0 1 power-on reset manual reset reset enable 0 1 note: * the chip is not reset internally, but tcnt and tcsr in wdt0 are reset. no internal reset when tcnt overflows * internal reset is generated when tcnt overflows watchdog overflow flag 0 1 [clearing condition] cleared by reading rstcsr when wovf = 1, then writing 0 to wovf [setting condition] when tcnt overflows (from hff to h00) in watchdog timer mode 768 smr0serial mode register 0 h'ff78 sci0 w a e 769 brr0bit rate register 0 h'ff79 sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 12.2.8, bit rate register (brr) : : : sets the serial transfer bit rate 770 scr0serial control register 0 h'ff7a sci0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled (normal reception performed) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. 0 1 clock enable 1 and 0 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: *1 *2 outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate. 771 tdr0transmit data register 0 h'ff7b sci0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission 772 ssr0serial status register 0 h'ff7c sci0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr framing error 0 1 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 0 1 [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt request and reads data to rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: * only 0 can be written, to clear the flag. [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr 773 rdr0receive data register 0 h'ff7d sci0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr0smart card mode register 0 h'ff7esci0 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : smart card data invert tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 reserved only 0 should be written to this bit smart card data transfer direction tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 774 smr1serial mode register 1 h'ff80 sci1 w a e 775 brr1bit rate register 1 h'ff81 sci1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 12.2.8, bit rate register (brr) : : : sets the serial transfer bit rate 776 scr1serial control register 1 h'ff82 sci1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : 0 1 transmit end interrupt enable transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled (normal reception performed) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 1 and 0 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: *1 *2 outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate. 777 tdr1transmit data register 1 h'ff83 sci1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission 778 ssr1serial status register 1 h'ff84 sci1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr framing error 0 1 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data is 1 when reception ends, and the stop bit is 0 0 1 [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt request and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: * only 0 can be written, to clear the flag. [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr 779 rdr1receive data register 1 h'ff85 sci1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr1smart card mode register 1 h'ff86 sci1 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : smart card data invert tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 reserved only 0 should be written to this bit smart card data transfer direction tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 780 smr2serial mode register 2 h'ff88 sci2 w a e 781 brr2bit rate register 2 h'ff89 sci2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 12.2.8, bit rate register (brr) : : : sets the serial transfer bit rate 782 scr2serial control register 2 h'ff8a sci2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled receive interrupt enable 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled (normal reception performed) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 1 and 0 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: *1 *2 outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate. 783 tdr2transmit data register 2 h'ff8b sci2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission 784 ssr2serial status register 2 h'ff8c sci2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr framing error 0 1 [clearing condition] when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 receive data register full 0 1 [clearing conditions] ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt request and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: * only 0 can be written, to clear the flag. [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt request and writes data to tdr [setting conditions] ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr 785 rdr2receive data register 2 h'ff8d sci2 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr2smart card mode register 2 h'ff8esci2 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : smart card data invert tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 reserved only 0 should be written to this bit smart card data transfer direction tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 port1port 1 register h'ffb0 port 1 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r note: * determined by the state of pins p17 to p10. state of port 1 pins bit initial value r/w : : : 786 port3port 3 register h'ffb2 port 3 7 undefined 6 p36 * r 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r note: * determined by the state of pins p36 to p30. state of port 3 pins bit initial value r/w : : : port4port 4 register h'ffb3 port 4 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r note: * determined by the state of pins p47 to p40. state of port 4 pins bit initial value r/w : : : port7port 7 register h'ffb6 port 7 7 p77 * r 6 p76 * r 5 p75 * r 4 p74 * r 3 p73 * r 0 p70 * r 2 p72 * r 1 p71 * r note: * determined by the state of pins p77 to p70. state of port 7 pins bit initial value r/w : : : port9port 9 register h'ffb8 port 9 7 r 6 p96 * r 5 r 4 r 3 r 0 r 2 r 1 r note: * determined by the state of pin p96. state of pin p96 bit initial value r/w : : : 787 portaport a register h'ffb9 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r note: * determined by the state of pins pa3 to pa0. state of port a pins bit initial value r/w : : : portbport b register h'ffba port b 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r note: * determined by the state of pins pb7 to pb0. state of port b pins bit initial value r/w : : : portcport c register h'ffbb port c 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r note: * determined by the state of pins pc7 to pc0. state of port c pins bit initial value r/w : : : portdport d register h'ffbc port d 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r note: * determined by the state of pins pd7 to pd0. state of port d pins bit initial value r/w : : : 788 porteport e register h'ffbd port e 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r note: * determined by the state of pins pe7 to pe0. state of port e pins bit initial value r/w : : : portfport f register h'ffbeport f 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r note: * determined by the state of pins pf7 to pf0. state of port f pins bit initial value r/w : : : portgport g register h'ffbf port g 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r note: * determined by the state of pins pg4 to pg0. state of port g pins bit initial value r/w : : : 789 appendix c i/o port block diagrams c.1 port 1 block diagrams r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr modes 4 to 6 c qd p1n * rdr1 rpor1 bus controller tpu module address output enable dma controller dma transfer acknowledge enable ! # $% & " " " ' pwm output enable output compare output/ pwm output input capture input wddr1 wdr1 rdr1 rpor1 n = 0 or 1 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 port 1 block diagram (pins p10 and p11) 790 r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr modes 4 to 6 c qd p1n * rdr1 rpor1 bus controller address output enable tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input wddr1 wdr1 rdr1 rpor1 n = 2 or 3 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-2 port 1 block diagram (pins p12 and p13) 791 r p1nddr c qd reset internal data bus wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 tpu module interrupt controller output compare output/ pwm output enable output compare output/ pwm output irq interrupt input input capture input * wddr1 wdr1 rdr1 rpor1 n = 4 or 6 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-3 port 1 block diagram (pins p14 and p16) 792 r p1nddr c qd reset internal data bus wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input * wddr1 wdr1 rdr1 rpor1 n = 5 or 7 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-4 port 1 block diagram (pins p15 and p17) 793 c.2 port 3 block diagrams r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial transmit enable serial transmit data p3ndr reset wodr3 r c qd p3nodr output enable signal open-drain control signal * wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 0 or 3 note: * priority order: serial transmit data output > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-5 port 3 block diagram (pins p30 and p33) 794 r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial receive data enable serial receive data p3ndr reset wodr3 r c qd p3nodr output enable signal open-drain control signal * wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 1 or 4 note: * priority order: serial receive data input > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-6 port 3 block diagram (pins p31 and p34) 795 r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial clock output 5 ( $ " 5 ( $(" enable p3ndr reset wodr3 r c qd p3nodr * serial clock input interrupt controller irq interrupt input output enable signal open-drain control signal wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 2 or 5 note: * priority order: serial clock input > serial clock output > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-7 port 3 block diagram (pins p32 and p35) 796 r p36ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p36 rdr3 rodr3 exirq 7 rpor3 p36dr reset wodr3 r c qd p36odr legend output enable signal open-drain control signal wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr figure c-8 port 3 block diagram (pin p36) 797 c.3 port 4 block diagram p4n rpor4 exirq0 to exirq6 internal data bus rpor4 n= 0 to 4, 6, or 7 : read port legend figure c-9 port 4 block diagram (pins p40 to p44, p46, and p47) p4n rpor4 a/d converter module internal data bus analog input rpor4 : read port legend figure c-10 port 4 block diagram (pin p45) 798 c.4 port 7 block diagrams r p70ddr c qd reset wddr7 internal data bus mode 7 modes 4 to 6 reset wdr7 r p70dr c qd p7n rdr7 rpor7 bus controller chip select dma controller wddr7 wdr7 rdr7 rpor7 n = 0 or 1 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend dma request input figure c-11 port 7 block diagram (pins p70 and p71) 799 r p7nddr c qd reset internal data bus wddr7 mode 7 reset wdr7 r p7ndr c qd p7n rdr7 rpor7 dma controller bus controller chip select dma transfer end enable dma transfer end * modes 4 to 6 wddr7 wdr7 rdr7 rpor7 n = 2 or 3 note: * priority order: compare match output > dr output : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-12 port 7 block diagram (pins p72 and p73) 800 r p74ddr c qd reset internal data bus wddr7 reset p74dtcoe wdr7 r p74dr c qd p74 rdr7 rpor7 manual reset input wddr7 wdr7 rdr7 rpor7 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend exdtce figure c-13 port 7 block diagram (pin p74) 801 r p7nddr c qd reset internal data bus wddr7 reset p75msoe or p76stpoe wdr7 r p7ndr c qd p7n rdr7 rpor7 manual reset input wddr7 wdr7 rdr7 rpor7 n = 5 or 6 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend exms or exmstp figure c-14 port 7 block diagram (pins p75 and p76) 802 r p77ddr c qd reset internal data bus wddr7 reset wdr7 r p77dr c qd p77 rdr7 rpor7 wddr7 wdr7 rdr7 rpor7 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-15 port 7 block diagram (pin p77) 803 c.5port 9 block diagram p96 rpor9 d/a converter module internal data bus output enable analog output rpor9 : read port 9 legend figure c-16 port 9 block diagram (pin p96) 804 c.6 port a block diagrams r pa0pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa0 rdra rodra rpora pa0dr reset wddra r c qd pa0ddr reset wodra rpcra r c qd pa0odr output enable signal modes 4 to 6 open-drain control signal * wddra wdra wodra wpcra : write to paddr : write to padr : write to paodr : write to papcr rdra rpora rodra rpcra : read padr : read port a : read paodr : read papcr legend note: * priority order: address output > dr output bus controller address output enable figure c-17 port a block diagram (pin pa0) 805 r pa1pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa1 rdra rodra rpora pa1dr reset wddra r c qd pa1ddr reset wodra rpcra r c qd pa1odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra note: * priority order: address output > serial transmit data > dr output : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial transmit enable serial transmit data figure c-18 port a block diagram (pin pa1) 806 r pa2pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa2 rdra rodra rpora pa2dr reset wddra r c qd pa2ddr reset wodra rpcra r c qd pa2odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial receive data enable serial receive data note: * priority order: address output > serial receive data input > dr output figure c-19 port a block diagram (pin pa2) 807 r pa3pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa3 rdra rodra rpora pa3dr reset wddra r c qd pa3ddr reset wodra rpcra r c qd pa3odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra note: * priority order: address output > serial clock input > serial clock output > dr output : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial clock output enable serial clock input enable serial clock input serial clock output figure c-20 port a block diagram (pin pa3) 808 c.7 port b block diagram r pbnpcr c qd reset internal data bus internal address bus wpcrb reset wdrb r c qd pbn rdrb rporb pbndr reset wddrb r c qd pbnddr rpcrb * output enable signal modes 4 to 6 wddrb wdrb wpcrb rdrb rporb rpcrb n = 0 to 7 note: * priority order: address output > dr output : write to pbddr : write to pbdr : write to pbpcr : read pbdr : read port b : read pbpcr legend bus controller address output enable figure c-21 port b block diagram (pins pb0 to pb7) 809 c.8 port c block diagram r pcnpcr c qd reset internal data bus internal address bus wpcrc reset wdrc r c qd pcn rdrc rporc pcndr reset wddrc r modes 4 and 5 * s c qd pcnddr rpcrc output enable signal mode 7 modes 4 to 6 wddrc wdrc wpcrc rdrc rporc rpcrc n = 0 to 7 : write to pcddr : write to pcdr : write to pcpcr : read pcdr : read port c : read pcpcr legend note: * set priority figure c-22 port c block diagram (pins pc0 to pc7) 810 c.9 port d block diagram reset r pdnpcr c qd reset internal upper data bus internal lower data bus wpcrd reset wdrd r c qd pdn rdrd external address upper write external address lower write rpord pdndr wddrd c qd pdnddr rpcrd mode 7 modes 4 to 6 external address write r external address upper read external address lower read legend wddrd wdrd wpcrd rdrd rpord rpcrd n = 0 to 7 : write to pdddr : write to pddr : write to pdpcr : read pddr : read port d : read pdpcr figure c-23 port d block diagram (pins pd0 to pd7) 811 c.10 port e block diagram reset r penpcr c qd reset internal upper data bus internal lower data bus wpcre reset wdre r c qd pen rdre rpore pendr wddre c qd penddr rpcre mode 7 modes 4 to 6 external address write r external address lower read legend wddre wdre wpcre rdre rpore rpcre n = 0 to 7 : write to peddr : write to pedr : write to pepcr : read pedr : read port e : read pepcr 8-bit bus mode figure c-24 port e block diagram (pins pe0 to pe7) 812 c.11 port f block diagrams r pf0ddr c qd reset internal data bus wddrf reset wdrf r c qd pf0 rdrf rporf bus request input interrupt controller irq interrupt input pf0dr bus controller brle output modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-25 port f block diagram (pin pf0) 813 r pf1ddr c qd reset internal data bus wddrf reset wdrf r c qd pf1 rdrf rporf pf1dr bus controller brle output bus request acknowledge output modes 4 to 6 legend wddrf wdrf rdrf rporf note: * priority order: bus request acknowledge output > dr output : write to pfddr : write to pfdr : read pfdr : read port f * figure c-26 port f block diagram (pin pf1) 814 r pf2ddr c qd reset internal data bus wddrf reset wdrf r c qd pf2 rdrf rporf wait input pf2dr bus controller wait enable modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-27 port f block diagram (pin pf2) 815 r pf3ddr c qd reset internal data bus wddrf reset wdrf r c qd pf3 rdrf rporf irq interrupt input pf3dr interrupt controller lwr output 16 bit bus mode bus controller modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-28 port f block diagram (pin pf3) 816 r pfnddr c qd reset internal data bus wddrf reset wdrf r c qd pfn rdrf rporf pfndr modes 4 to 6 mode 7 pf4: hwr output pf5: rd output pf6: as output bus controller modes 4 to 6 legend wddrf wdrf rdrf rporf n = 4 to 6 : write to pfddr : write to pfdr : read pfdr : read port f figure c-29 port f block diagram (pins pf4 to pf6) 817 r s pf7ddr c qd reset internal data bus modes 4 to 6 * wddrf reset wdrf r c qd pf7 rdrf rporf pf7dr ? legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f note: * set priority figure c-30 port f block diagram (pin pf7) 818 c.12 port g block diagrams r pg0ddr c qd reset internal data bus wddrg reset wdrg r c qd pg0 rdrg rporg irq interrupt input pg0dr interrupt controller legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g figure c-31 port g block diagram (pin pg0) 819 r pg1ddr c qd reset internal data bus wddrg reset wdrg r c qd pg1 rdrg rporg irq interrupt input pg1dr interrupt controller legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-32 port g block diagram (pin pg1) 820 r pgnddr c qd wddrg reset reset internal data bus wdrg r c qd pgn rdrg rporg pgndr legend wddrg wdrg rdrg rporg n = 2 or 3 : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-33 port g block diagram (pins pg2 and pg3) 821 r s pg4ddr c qd wddrg reset reset internal data bus modes 4 and 5 modes 6 and 7 wdrg r c qd pg4 rdrg rporg pg4dr legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-34 port g block diagram (pin pg4) 822 appendix d pin states d.1 port states in each processing state table d-1 i/o port states in each processing state port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode p17 to p14 4 to 7 t keep t keep keep i/o port p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 7 t keep t keep keep i/o port address output selected by aen bit 4 to 6 t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t keep t keep keep i/o port p10/tioca0/a20 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port port 3 4 to 7 t keep t keep keep i/o port port 4 4 to 7 t t t t t input port p77 to p74 4 to 7 t keep t keep keep i/o port p73/ cs7 p72/ cs6 p71/ cs5 p70/ cs4 7 4 to 6 t t keep keep t t keep [ddrope= 0] t [ddrope= 1] h keep t i/o port [ddr = 0] input port [ddr = 1] cs7 to cs4 p96/da0 4 to 7 t t t [daoen= 1] keep [daoen= 0] t keep input port port a 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port 823 port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode port b 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port port c 4, 5 l keep t [ope= 0] t [ope= 1] keep t address output 6 t keep t [ddrope= 0] t [ddrope= 1] keep t [ddr = 0] input port [ddr = 1] address output 7 t keep t keep keep i/o port port d 4 to 6 t t t t t data bus 7 t keep t keep keep i/o port port e 8-bit bus 4 to 6 t keep t keep keep i/o port 16-bit bus 4 to 6 t t t t t data bus 7 t keep t keep keep i/o port pf7/? 4 to 6 clock output [[ddr = 0] input port [ddr = 1] clock output t [ddr= 0] input port [ddr= 1] h [ddr= 0] input port [ddr= 1] clock output [ddr= 0] input port [ddr= 1] clock output 7 t keep t [ddr= 0] input port [ddr= 1] h [ddr= 0] input port [ddr= 1] clock output [ddr= 0] input port [ddr= 1] clock output pf6/ as , pf5/ rd , pf4/ hwr 4 to 6 h h t [ope= 0] t [ope= 1] h t as , rd , hwr 7 t keep t keep keep i/o port pf3/ lwr / irq3 7 t keep t keep keep i/o port 8-bit bus 16-bit bus 4 to 6 4 to 6 (mode 4) h (modes 5 and 6) t keep h t t keep [ope= 0] t [ope= 1] h keep t i/o port lwr 824 port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode pf2/ wait 4 to 6 t keep t [waite= 0] keep [waite= 1] t [waite= 0] keep [waite= 1] t [waite= 0] i/o port [waite= 1] wait 7 t keep t keep keep i/o port pf1/ back 4 to 6 t keep t [brle= 0] keep [brle= 1] h l [brle= 0] i/o port [brle= 1] back 7 t keep t keep keep i/o port pf0/ breq / ireq2 4 to 6 t keep t [brle= 0] keep [brle= 1] t t [brle= 0] i/o port [brle= 1] breq 7 t keep t keep keep i/o port pg4/ cs0 4, 5 6 h t keep t [ddrope= 0] t [ddrope= 1] h t [ddr = 0] input port [ddr = 1] cs0 (in sleep mode and subsleep mode: h) 7 t keep t keep keep i/o port pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 4 to 6 t keep t [ddrope= 0] t [ddrope= 1] h t [ddr= 0] input port [ddr= 1] cs1 to cs3 7 t keep t keep keep i/o port pg0/ irq6 4 to 7 t keep t keep keep i/o port legend: h: high level l: low level t: high impedance keep: input port becomes high-impedance, output port retains state ddr data direction register ope: output port enable waite: wait input enable brle: bus release enable note: * l in modes 4 and 5 (address output) 825 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low at least 10 states before the stby signal goes low, as shown below. res must remain low until stby signal goes low (delay from stby low to res high: 0 ns or more). stby res t 2 0ns t 1 10t cyc figure e-1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode drive the res signal low and the nmi signal high approximately 100 ns or more before stby goes high to execute a power-on reset. stby res t osc t 100ns figure e-2 timing of recovery from hardware standby mode 826 appendix f product code lineup table f-1 h8s/2214 product code lineup product type product code mark code package h8s/2214 mask rom version hd6432214 6432214(***)te 100-pin tqfp (tfp-100b) 6432214(***)tf 100-pin tqfp (tfp-100g) 6432214(***)bp 112-pin tfbga (tbp-112) f-ztat version hd64f2214 64f2214te16 100-pin tqfp (tfp-100b) 64f2214tf16 100-pin tqfp (tfp-100g) 64f2214bp 112-pin tfbga (tbp-112) [explanation of symbol] (***) indicates rom code. 827 appendix g package dimensions figures g-1, g-2, and g-3 show the h8s/2214 package dimensions. hitachi code jedec eiaj weight (reference value) tfp-100b conforms 0.5 g unit: mm *dimension including the plating thickness base material dimension 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max *0.17 0.05 0 C 8 75 51 125 76 100 26 50 m *0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 figure g-1 tfp-100b package dimensions 828 hitachi code jedec eiaj weight (reference value) tfp-100g conforms 0.4 g unit: mm *dimension including the plating thickness base material dimension 14.0 0.2 12 0.07 0.10 0.5 0.1 14.0 0.2 0.4 1.20 max *0.17 0.05 0 C 8 75 51 125 76 100 26 50 m *0.18 0.05 1.0 1.2 0.16 0.04 0.15 0.04 1.00 0.10 0.10 figure g-2 tfp-100g package dimensions 829 10.0 0.4 0.05 0.2 0.1 9.6 0.1 10.0 c c 0.20 a 4 1.2 max 0.3 c b 0.8 11 10 9 8 7 6 5 4 3 2 1 a b c d e f g h j k l 0.8 1.0 1.0 b a c 0.08 ab 112 0.5 0.05 details of the part a m 0.3 c a c hitachi code jedec eiaj weight (reference value) tbp-112 0.19 g unit: mm figure g-3 tbp-112 package dimensions 830 h8s/2214, h8s/2214 f-ztat? hardware manual publication date: 1st edition, april 2000 2nd edition, july 2001 published by: customer service division semiconductor & integrated circuits hitachi, ltd. edited by: technical documentation group hitachi kodaira semiconductor co., ltd. co py ri g ht ? hitachi, ltd., 2000. all ri g hts reserved. printed in ja p an. |
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